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april 2011 doc id 14611 rev 8 1/130 1 stm32f103xc stm32f103xd stm32f103xe high-density performance line ar m-based 32-bit mcu with 256 to 512kb flash, usb, can, 11 timers, 3 adcs, 13 communication interfaces features core: arm 32-bit cortex?-m3 cpu ? 72 mhz maximum frequency, 1.25 dmips/mhz (dhrystone 2.1) performance at 0 wait state memory access ? single-cycle multiplication and hardware division memories ? 256 to 512 kbytes of flash memory ? up to 64 kbytes of sram ? flexible static memory controller with 4 chip select. supports compact flash, sram, psram, nor and nand memories ? lcd parallel interface, 8080/6800 modes clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr, and programmable voltage detector (pvd) ? 4-to-16 mhz crystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc with calibration ? 32 khz oscillator for rtc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers 3 12-bit, 1 s a/d converters (up to 21 channels) ? conversion range: 0 to 3.6 v ? triple-sample and hold capability ? temperature sensor 2 12-bit d/a converters dma: 12-channel dma controller ? supported peripherals: timers, adcs, dac, sdio, i 2 ss, spis, i 2 cs and usarts debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m3 embedded trace macrocell? up to 112 fast i/o ports ? 51/80/112 i/os, all mappable on 16 external interrupt vectors and almost all 5 v-tolerant up to 11 timers ? up to four 16-bit timers, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? 2 16-bit motor control pwm timers with dead-time generation and emergency stop ? 2 watchdog timers (independent and window) ? systick timer: a 24-bit downcounter ? 2 16-bit basic timers to drive the dac up to 13 communication interfaces ? up to 2 i 2 c interfaces (smbus/pmbus) ? up to 5 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 3 spis (18 mbit/s), 2 with i 2 s interface multiplexed ? can interface (2.0b active) ? usb 2.0 full speed interface ? sdio interface crc calculation unit, 96-bit unique id ecopack ? packages table 1. device summary reference part number stm32f103xc stm32f103rc stm32f103vc stm32f103zc stm32f103xd stm32f103rd stm32f103vd stm32f103zd stm32f103xe stm32f103re stm32f103ze stm32f103ve fbga lqfp64 10 10 mm, lqfp100 14 14 mm, lqfp144 20 20 mm lfbga100 10 10 mm lfbga144 10 10 mm wlcsp64 www.st.com
contents stm32f103xc, stm32f103xd, stm32f103xe 2/130 doc id 14611 rev 8 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 arm ? cortex?-m3 core with embedded flash and sram . . . . . . . . . 15 2.3.2 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 fsmc (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 lcd parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 rtc (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.19 universal synchronous/asynchronous receiver transmitters (usarts) 21 2.3.20 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.21 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 sdio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 adc (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.28 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
stm32f103xc, stm32f103xd, stm32f103xe contents doc id 14611 rev 8 3/130 2.3.29 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.30 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43 5.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 43 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.10 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.12 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 84 5.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3.16 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.3.18 can (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.19 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
contents stm32f103xc, stm32f103xd, stm32f103xe 4/130 doc id 14611 rev 8 5.3.20 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 121 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
stm32f103xc, stm32f103xd, stm32f103xe list of tables doc id 14611 rev 8 5/130 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f103xc, stm32f103xd and stm32f103xe features and peripheral counts . . . . 11 table 3. stm32f103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. high-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. high-density stm32f103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6. fsmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 9. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 10. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 11. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 12. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 13. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 table 14. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 15. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 16. maximum current consumption in sleep mode, code running from flash or ram. . . . . . . 47 table 17. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 48 table 18. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 19. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 20. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 21. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 22. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 23. hse 4-16 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 table 24. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 25. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 26. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 27. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 28. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 29. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 30. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 31. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . . 64 table 32. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . . 65 table 33. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 34. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 35. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 36. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 37. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 38. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 39. switching characteristics for pc card/cf read and write cycles . . . . . . . . . . . . . . . . . . . . 79 table 40. switching characteristics for nand flash read and write cycles . . . . . . . . . . . . . . . . . . . . 82 table 41. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 42. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 43. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 44. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
list of tables stm32f103xc, stm32f103xd, stm32f103xe 6/130 doc id 14611 rev 8 table 45. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 46. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 47. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 48. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 49. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 50. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 51. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 52. scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 53. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 54. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 55. sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 56. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 57. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 58. usb: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02 table 59. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 60. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 61. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 table 62. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 63. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 64. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 65. recommended pcb design rules (0.80/0.75 mm pitch bga) . . . . . . . . . . . . . . . . . . . . . 112 table 66. lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 67. lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 68. wlcsp, 64-ball 4.466 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 69. recommended pcb design rules (0.5mm pitch bga) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 70. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 117 table 71. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 118 table 72. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 119 table 73. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 74. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
stm32f103xc, stm32f103xd, stm32f103xe list of figures doc id 14611 rev 8 7/130 list of figures figure 1. stm32f103xc, stm32f103xd and stm32f103xe performance line block diagram . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. stm32f103xc and stm32f103xe performance line bga144 ballout . . . . . . . . . . . . . . . 24 figure 4. stm32f103xc and stm32f103xe performance line bga100 ballout . . . . . . . . . . . . . . . 25 figure 5. stm32f103xc and stm32f103xe performance line lqfp144 pinout. . . . . . . . . . . . . . . 26 figure 6. stm32f103xc and stm32f103xe performance line lqfp100 pinout. . . . . . . . . . . . . . . 27 figure 7. stm32f103xc and stm32f103xe performance line lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 8. stm32f103xc and stm32f103xe performance line wlcsp64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 13. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled . . . . . . . . . . . . . . . . . 46 figure 15. typical current consumption in run mode versus frequency (at 3.6 v)- code with data processing running from ram, peripherals disabled . . . . . . . . . . . . . . . . 46 figure 16. typical current consumption on v bat with rtc on vs. temperature at different v bat values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 17. typical current consumption in stop mode with regulator in run mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 18. typical current consumption in stop mode with regulator in low-power mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 19. typical current consumption in standby mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 20. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 21. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 22. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 23. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 24. asynchronous non-multiplexed sram/psram/nor read waveforms . . . . . . . . . . . . . . . 64 figure 25. asynchronous non-multiplexed sram/psram/nor write waveforms . . . . . . . . . . . . . . . 65 figure 26. asynchronous multiplexed psram/nor read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 27. asynchronous multiplexed psram/nor write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 28. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 29. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 30. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 31. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 32. pc card/compactflash controller waveforms for common memory read access . . . . . . . 75 figure 33. pc card/compactflash controller waveforms for common memory write access . . . . . . . 76 figure 34. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 35. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 36. pc card/compactflash controller waveforms for i/o space read access . . . . . . . . . . . . . 78 figure 37. pc card/compactflash controller waveforms for i/o space write access . . . . . . . . . . . . . 79 figure 38. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
list of figures stm32f103xc, stm32f103xd, stm32f103xe 8/130 doc id 14611 rev 8 figure 39. nand controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 40. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 81 figure 41. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 82 figure 42. standard i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 43. standard i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 figure 44. 5 v tolerant i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 45. 5 v tolerant i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 46. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 47. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 48. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 49. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 50. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 51. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 52. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 53. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 54. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 55. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 56. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 57. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 58. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 59. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 106 figure 60. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 107 figure 61. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 62. bga pad footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 63. lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 64. lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 65. wlcsp, 64-ball 4.466 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 66. bga pad footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 67. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 68. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 69. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 118 figure 70. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 71. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 119 figure 72. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 73. lqfp100 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
stm32f103xc, stm32f103xd, stm32f103xe introduction doc id 14611 rev 8 9/130 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f103xc, stm32f103xd and stm32f103xe high-density performance line microcontrollers. for more details on the whole stmicroelectronics stm32f103xx family, please refer to section 2.2: full compatib ility throughou t the family . the high-density stm32f103xx datasheet should be read in conjunction with the stm32f10xxx reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f10xxx flash programming manual. the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/ .
description stm32f103xc, stm32f103xd, stm32f103xe 10/130 doc id 14611 rev 8 2 description the stm32f103xc, stm32f103xd and stm32f103xe performance line family incorporates the high-performance arm ? cortex?-m3 32-bit risc core operating at a 72 mhz frequency, high-speed embedded memori es (flash memory up to 512 kbytes and sram up to 64 kbytes), and an extensive range of enhanced i/os and peripherals connected to two apb buses. all devices offer three 12-bit adcs, four general-purpose 16- bit timers plus two pwm timers, as well as standard and advanced communication interfaces: up to two i 2 cs, three spis, two i 2 ss, one sdio, five usarts, an usb and a can. the stm32f103xx high-density performance line family operates in the ?40 to +105 c temperature range, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. these features make the stm32f103xx high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, pc and gaming peripherals, gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems video intercom, and hvac.
stm32f103xc, stm32f103xd, stm32f103xe description doc id 14611 rev 8 11/130 2.1 device overview the stm32f103xx high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. depe nding on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. figure 1 shows the general block diagram of the device family. table 2. stm32f103xc, stm32f103xd and stm32f103xe features and peripheral counts peripherals stm32f103rx s tm32f103vx stm32f103zx flash memory in kbytes 256 384 512 256 384 512 256 384 512 sram in kbytes 48 64 (1) 1. 64 kb ram for 256 kb flash are available on devices delivered in csp packages only. 48 64 48 64 fsmc no yes (2) 2. for the lqfp100 and bga100 packages, only fsmc bank1 and bank2 are avai lable. bank1 can only support a multiplexed nor/psram memory using the ne 1 chip select. bank2 can only support a 16- or 8-bit nand flash memory using the nce2 chip select. the interrupt line cannot be used since port g is not available in this package. ye s timers general-purpose 4 advanced-control 2 basic 2 comm spi(i 2 s) (3) 3. the spi2 and spi3 interfaces give the flexibility to wo rk in an exclusive way in either the spi mode or the i 2 s audio mode. 3(2) i 2 c2 usart 5 usb 1 can 1 sdio 1 gpios 51 80 112 12-bit adc number of channels 3 16 3 16 3 21 12-bit dac number of channels 2 2 cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c (see ta bl e 1 0 ) junction temperature: ?40 to + 125 c (see ta b l e 1 0 ) package lqfp64, wlcsp64 lqfp 100, bga100 lqfp144, bga144
description stm32f103xc, stm32f103xd, stm32f103xe 12/130 doc id 14611 rev 8 figure 1. stm32f103xc, stm32f103xd and stm32f103xe performance line block diagram 1. t a = ?40 c to +85 c (suffix 6, see table 74 ) or ?40 c to +105 c (suffix 7, see table 74 ), junction temperature up to 105 c or 125 c, respectively. 2. af = alternate function on i/o port pin. pa[15:0] ext.it 112af ahb2 2x( 8 x16 b it) wkup f m a x : 4 8 /72 mhz v ss i2c2 gp dma1 tim2 tim 3 xtal 3 2khz fl as h 512 k b yte s v dd b a ck u p interf a ce tim4 b us m a trix 64 b it rtc rc 8 mhz cortex-m 3 cpu d bus o b l fl as h interf a ce u s art 2 s pi2 / i2 s 2 b a ck u p reg tim1 i2c1 rx, tx, ct s , r t s , u s art 3 rc 40 khz s t a nd b y iwdg @ v bat por / pdr @v dda v bat =1. 8 v to 3 .6 v ck as af rx, tx , ct s , rt s , ck as af nvic s pi1 interf a ce @v dda pvd int apb2 awu tim 8 2x( 8 x16 b it) s pi 3 / i2 s3 uart4 rx,tx as af uart5 rx,tx as af tim5 pll @v dda f s mc dac_out1 as af dac_out2 as af s ram 64 kb gp dma2 tim6 tim7 njtr s t jtdi jtck/ s wclk jtm s / s wdio jtdo as af a[25:0] d[15:0] clk noe nwe ne[4:1] nbl[1:0] nwait nl (or nadv) as af 7 ch a nnel s 5 ch a nnel s gpio port a gpio port b gpio port c gpio port d gpio port e gpio port f gpio port g u s art1 temp. s en s or 12- b it adc1 12- b it adc2 12- b it adc 3 if if if pb[15:0] pc[15:0] pd[15:0] pe[15:0] pf[15:0] pg[15:0] 4 ch a nnel s 3 compl. ch a nnel s bkin, etr as af 4 ch a nnel s 3 compl. ch a nnel s bkin, etr as af mo s i, mi s o, s ck, n ss as af rx, tx, ct s , rt s , ck as af 8 adc12 3 _in s common to the 3 adc s 8 adc12_in s common to adc1 & adc2 5 adc 3 _in s on adc 3 v ref+ v ref? @ v dda apb2: fm a x = 4 8 /72 mhz apb1 tr a ce controller p bus i bus s y s tem re s et & clock control pclk1 pclk2 hclk fclk power volt. reg. 3 . 3 v to 1. 8 v su pply su pervi s ion @v dd por re s et nr s t v dda v ss a o s c_in o s c_out @v dd xtal o s c 4-16 mhz o s c 3 2_in o s c 3 2_out tamper-rtc/ alarm/ s econd out 4 ch a nnel s , etr as af 4 ch a nnel s , etr as af 4 ch a nnel s , etr as af 4 ch a nnel s as af mo s i/ s d, mi s o s ck/ck, mck, n ss /w s as af mo s i/ s d, mi s o s ck/ck, mck, n ss /w s as af s cl, s da, s mba as af s cl, s da, s mba as af b xcan device u s b 2.0 f s device u s bdp/can_tx u s bdm/can_rx s ram 512 b wwdg a i14666f apb1: f m a x = 24/ 3 6 mhz traceclk traced[0: 3 ] as a s s w/jtag tpiu tr a ce/trig s dio d[7:0] cmd ck as af ahb: fm a x = 4 8 /72 mhz ahb2 12 b it dac1 if if if 12 b it dac 2
stm32f103xc, stm32f103xd, stm32f103xe description doc id 14611 rev 8 13/130 figure 2. clock tree 1. when the hsi is used as a pll clock input, the maxi mum system clock frequency t hat can be achieved is 64 mhz. 2. for the usb function to be available, both hse and pll must be enabled, with the usbclk at 48 mhz. 3. to have an adc conversion time of 1 s, apb2 must be at 14 mhz, 28 mhz or 56 mhz. hse osc 4-16 mhz osc_in osc_out osc32_in osc32_out lse osc 32.768 khz hsi rc 8 mhz lsi rc 40 khz to independent watchdog (iwdg) pll x2, x3, x4 pllmul hse = high speed external clock signal lse = low speed external clock signal lsi = low speed internal clock signal hsi = high speed internal clock signal legend: mco clock output main pllxtpre /2 ..., x16 ahb prescaler /1, 2..512 /2 pllclk hsi hse apb1 prescaler /1, 2, 4, 8, 16 adc prescaler /2, 4, 6, 8 adcclk pclk1 hclk pllclk to ahb bus, core, memory and dma usbclk to usb interface usb prescaler /1, 1.5 to adc1, 2 or 3 lse lsi hsi /128 /2 hsi hse peripherals to apb1 peripheral clock enable (20 bits) enable (6 bits) peripheral clock apb2 prescaler /1, 2, 4, 8, 16 pclk2 tim1 & 8 timers to tim1 and tim8 peripherals to apb2 peripheral clock enable (15 bits) enable (2 bit) peripheral clock 48 mhz 72 mhz max 72 mhz 72 mhz max 36 mhz max to rtc pllsrc sw mco css to cortex system timer /8 clock enable (4 bits) sysclk max rtcclk rtcsel[1:0] timxclk timxclk iwdgclk sysclk fclk cortex free running clock /2 tim2,3,4,5,6,7 to tim2,3,4,5,6 and 7 to sdio ahb interface peripheral clock enable hclk/2 to fsmc fsmcclk to sdio peripheral clock enable peripheral clock enable to i2s3 to i2s2 peripheral clock enable peripheral clock enable i2s3clk i2s2clk sdioclk ai14752b if (apb1 prescaler =1) x1 else x2 if (apb2 prescaler =1) x1 else x2 flitfclk to flash programming interface
description stm32f103xc, stm32f103xd, stm32f103xe 14/130 doc id 14611 rev 8 2.2 full compatibility throughout the family the stm32f103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. in the reference manual, the stm32f103x4 and stm32f103x6 are identified as low-density devices, the stm32f103x8 and stm32f103xb are referred to as medium-density devices and the stm32f 103xc, stm32f103xd and stm32f103xe are referred to as high-density devices. low-density and high-density devices are an extension of the stm32f103x8/b medium- density devices, they are specified in the stm32f103x4/6 and stm32f103xc/d/e datasheets, respectively. low-density devices feature lower flash memory and ram capacities, less timers and peripherals. high-density devices have higher flash memory and ram capacities, and additional peripherals like sdio, fsmc, i 2 s and dac while remaining fully compatible with the other members of the family. the stm32f103x4, stm32f103x6, stm32f103xc, stm32f103xd and stm32f103xe are a drop-in replacement for the stm32f103x8/b devices, allowing the user to try different memory densities and providi ng a greater degree of freedom during the development cycle. moreover, the stm32f103xx performance line fam ily is fully compatible with all existing stm32f101xx access line and stm32f102xx usb access line devices. table 3. stm32f103xx family pinout low-density devices medium-density devices high-density devices 16 kb flash 32 kb flash (1) 1. for orderable part numbers that do not show the a in ternal code after the temper ature range code (6 or 7), the reference datasheet for electric al characteristics is that of the stm32f103x8/b medium-density devices. 64 kb flash 128 kb flash 256 kb flash 384 kb flash 512 kb flash 6 kb ram 10 kb ram 20 kb ram 20 kb ram 48 ram 64 kb ram 64 kb ram 144 5 usarts 4 16-bit timers, 2 basic timers 3 spis, 2 i 2 ss, 2 i2cs usb, can, 2 pwm timers 3 adcs, 2 dacs, 1 sdio fsmc (100- and 144-pin packages (2) ) 2. ports f and g are not available in dev ices delivered in 100-pin packages. 100 3 usarts 3 16-bit timers 2 spis, 2 i 2 cs, usb, can, 1 pwm timer 2 adcs 64 2 usarts 2 16-bit timers 1 spi, 1 i 2 c, usb, can, 1 pwm timer 2 adcs 48 36
stm32f103xc, stm32f103xd, stm32f103xe description doc id 14611 rev 8 15/130 2.3 overview 2.3.1 arm ? cortex?-m3 core with embedded flash and sram the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. with its embedded arm core, stm32f103xc, stm32f103xd and stm32f103xe performance line family is compatib le with all arm tools and software. figure 1 shows the general block diagram of the device family. 2.3.2 embedded flash memory up to 512 kbytes of embedded flash is available for storing programs and data. 2.3.3 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.3.4 embedded sram up to 64 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. 2.3.5 fsmc (flexible static memory controller) the fsmc is embedded in the stm32f103xc, stm32f103xd and stm32f103xe performance line family. it has four chip select outputs supporting the following modes: pc card/compact flash, sr am, psram, nor and nand. functionality overview: the three fsmc interrupt lines are ored in order to be connected to the nvic write fifo code execution from external memory except for nand flash and pc card the targeted frequency, f clk , is hclk/2, so external access is at 36 mhz when hclk is at 72 mhz and external access is at 24 mhz when hclk is at 48 mhz
description stm32f103xc, stm32f103xd, stm32f103xe 16/130 doc id 14611 rev 8 2.3.6 lcd parallel interface the fsmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel interface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high- performance solutions using external controllers with dedicated acceleration. 2.3.7 nested vectored interrupt controller (nvic) the stm32f103xc, stm32f103xd and stm32f103xe performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.8 external interrupt /event controller (exti) the external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 cloc k period. up to 112 gp ios can be connected to the 16 external interrupt lines. 2.3.9 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an ex ternal 4-16 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow the configuration of the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. the maximum frequency of the ahb and the high speed apb domains is 72 mhz. the maximum allowed frequency of the low speed apb domain is 36 mhz. see figure 2 for details on the clock tree.
stm32f103xc, stm32f103xd, stm32f103xe description doc id 14611 rev 8 17/130 2.3.10 boot modes at startup, boot pins are used to select one of three boot options: boot from user flash: you have an option to boot from any of two memory banks. by default, boot from flash memory bank 1 is selected. you can choose to boot from flash memory bank 2 by setting a bit in the option bytes. boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1. 2.3.11 power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll (minimum voltage to be applie d to vdda is 2.4 v when the adc or dac is used). v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.8 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 12: power supply scheme . 2.3.12 power supply supervisor the device has an integrated power-on reset (por)/power-down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remains in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. refer to table 12: embedded reset and power control block characteristics for the values of v por/pdr and v pvd . 2.3.13 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. mr is used in the nominal regulation mode (run) lpr is used in the stop modes. power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode.
description stm32f103xc, stm32f103xd, stm32f103xe 18/130 doc id 14611 rev 8 2.3.14 low-power modes the stm32f103xc, stm32f103xd and stm32f103xe performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm or the usb wakeup. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 2.3.15 dma the flexible 12-channel general-purpose dmas (7 channels for dma1 and 5 channels for dma2) are able to manage memory-to-memory, peripheral-to-memory and memory-to- peripheral transfers. the two dma controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose, basic and advanced-control timers timx, dac, i 2 s, sdio and adc. 2.3.16 rtc (real-time cl ock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, and they are not reset when the device wakes up from the standby mode. the real-time clock provides a set of continuo usly running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a
stm32f103xc, stm32f103xd, stm32f103xe description doc id 14611 rev 8 19/130 periodic interrupt. it is clocke d by a 32.768 khz external crysta l, resonator or oscillator, the internal low power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. the rtc features a 32-bit programmable counter for long term measurement using the compare register to generate an alarm. a 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. 2.3.17 timers and watchdogs the high-density stm32f103xx performance line devices include up to two advanced- control timers, up to four general-purpose timers, two basic timers, two watchdog timers and a systick timer. ta bl e 4 compares the features of the advanced-control, general-purpose and basic timers. advanced-control timers (tim1 and tim8) the two advanced-control timers (tim1 and tim8) can each be seen as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead-times. they can also be seen as a complete general-purpose timer. the 4 independent channels can be used for: input capture output compare pwm generation (edge or center-aligned modes) one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switch driven by these outputs. many features are shared with those of the general-purpose tim timers which have the same architecture. the advanced-control timer can therefore work together with the tim timers via the timer link feature for synchronization or event chaining. table 4. high-density timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s tim2, tim3, tim4, tim5 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim6, tim7 16-bit up any integer between 1 and 65536 ye s 0 n o
description stm32f103xc, stm32f103xd, stm32f103xe 20/130 doc id 14611 rev 8 general-purpose timers (timx) there are up to 4 synchronizable general-purpose timers (tim2, tim3, tim4 and tim5) embedded in the stm32f103xc, stm32f103xd and stm32f103xe performance line devices. these timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, pwm or one- pulse mode output. this gives up to 16 input captures / output compares / pwms on the largest packages. the general-purpose timers can work together with the advanced-control timer via the timer link feature for synchronization or event chaining. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. they all have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. basic timers tim6 and tim7 these timers are mainly used for dac trigger generation. they can also be used as a generic 16-bit time base. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. window watchdog the window watchdog is based on a 7-bit downcoun ter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source 2.3.18 i2c bus up to two i2c bus interfaces can operate in multimaster and slave modes. they can support standard and fast modes. they support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus.
stm32f103xc, stm32f103xd, stm32f103xe description doc id 14611 rev 8 21/130 2.3.19 universal sync hronous/asynchronous receiver transmitters (usarts) the stm32f103xc, stm32f103xd and stm32f103xe performance line embeds three universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3) and two universal asynchronous receiver transmitters (uart4 and uart5). these five interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 interface is able to communicate at speeds of up to 4.5 mbit/s. the other available interfaces communicate at up to 2.25 mbit/s. usart1, usart2 and usart3 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 complia nt) and spi-like communication capability. all interfaces can be served by the dma controller except for uart5. 2.3.20 serial perip heral interface (spi) up to three spis are able to communicate up to 18 mbits/s in slave and master modes in full-duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. 2.3.21 inter-integrated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available, that can be operated in master or slave mode. these interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. audio sampling frequencies from 8 khz up to 48 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. 2.3.22 sdio an sd/sdio/mmc host interface is availabl e, that supports mu ltimediacard system specification version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz in 8-bit mode, and is compliant with sd memory card specifications version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdio/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is also fully compliant with the ce-ata digital protocol rev1.1. 2.3.23 controller area network (can) the can is compliant with specifications 2.0a and b (active) with a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks.
description stm32f103xc, stm32f103xd, stm32f103xe 22/130 doc id 14611 rev 8 2.3.24 universal serial bus (usb) the stm32f103xc, stm32f103xd and stm32f103xe performance line embed a usb device peripheral compatible with the usb full-speed 12 mbs. the usb interface implements a full-speed (12 mbit/s) function interface. it has software-configurable endpoint setting and suspend/resume support. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator). 2.3.25 gpios (genera l-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current- capable except for analog inputs. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 2.3.26 adc (analog to digital converter) three 12-bit analog-to-digital converters are embedded into stm32f103xc, stm32f103xd and stm32f103xe performance line devices and each adc shares up to 21 external channels, performing conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: simultaneous sample and hold interleaved sample and hold single shunt the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) and the advanced-control timers (tim1 and tim8) can be internally connected to the adc start trigger and injection trigger, respectively, to allow the applicatio n to synchronize a/d conversion and timers. 2.3.27 dac (digital-t o-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.
stm32f103xc, stm32f103xd, stm32f103xe description doc id 14611 rev 8 23/130 this dual digital interface supports the following features: two dac converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channel independent or simultaneous conversions dma capability for each channel external triggers for conversion input voltage reference v ref+ eight dac trigger inputs are used in the stm32f103xc, stm32f103xd and stm32f103xe performance line family. the dac channels are triggered through the timer update outputs that are also connected to different dma channels. 2.3.28 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.29 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.3.30 embedded trace macrocell? the arm ? embedded trace macrocell provides a greater visibilit y of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f10xxx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools.
pinouts and pin descriptions stm32f103xc, stm32f103xd, stm32f103xe 24/130 doc id 14611 rev 8 3 pinouts and pin descriptions figure 3. stm32f103xc and stm32f103xe performance line bga144 ballout ai1479 8b v dd_7 pc 3 pc2 pf6 v dd_6 v ss _4 pf 8 h v dd_1 d pg1 3 pg14 pe6 pe5 c pg10 pg11 v dd_5 pb 8 nr s t b pg12 pg15 pc15- o s c 3 2_out pb9 a 8 7 6 5 4 3 2 1 v bat o s c_in o s c_out v ss _5 g f e pf7 pc0 pf0 pf1 pf2 v ss _10 pg9 pf4 pf 3 v ss _ 3 pf5 v dd_ 8 v dd_ 3 v dd_4 v ss _ 8 pe4 pb5 pb6 boot0 pb7 v ss _11 pf10 pc1 v dd_11 v dd_10 pf9 10 9 k j v ss _2 pd 3 pd4 pd1 pc12 pc11 pd5 pd2 pd0 v dd_9 v ss _9 v dd_2 pg1 pc5 pa5 pe9 pb2/ boot1 pc4 pa4 pe10 pg0 pf1 3 v ref? pe12 v ss a pa1 pe1 3 pa0-wkup pd9 pd10 pg4 pd1 3 12 11 pg 8 pa10 nc pa9 pa11 pa12 pc10 pc9 pa 8 pc7 pc6 pc 8 pd14 pg 3 pg2 pd15 m l pf15 pb1 pa7 pe7 pf12 pb0 pa6 pe 8 pf14 pf11 v dda pe14 v ref+ pa 3 pe15 pa2 pb10 pd 8 pd12 pb11 pb12 pb14 pb15 pb1 3 pc1 3 - tamper-rtc pe 3 pe2 pe1 pe0 pb4 jtr s t pb 3 jtdo pd6 pd7 pa15 jtdi pa14 jtck pa1 3 jtm s pe11 v ss _6 v ss _7 v ss _1 pg7 pd11 pg5 pg6 pc14- o s c 3 2_in
stm32f103xc, stm32f103xd, stm32f103xe pinouts and pin descriptions doc id 14611 rev 8 25/130 figure 4. stm32f103xc and stm32f103xe performance line bga100 ballout ai14601c pe10 pc14- o s c 3 2_in pc5 pa5 pc 3 pb4 pe15 pb2 pc4 pa4 h pe14 pe11 pe7 d pd4 pd 3 pb 8 pe 3 c pd0 pc12 pe5 pb5 pc0 pe2 b pc11 pd2 pc15- o s c 3 2_out pb7 pb6 a 8 7 6 5 4 3 2 1 v ss _5 o s c_in o s c_out v dd_5 g f e pc1 v ref? pc1 3 - tamper-rtc pb9 pa15 pb 3 pe4 pe1 pe0 v ss _1 pd1 pe6 nr s t pc2 v ss _ 3 v ss _4 nc v dd_ 3 v dd_4 pb15 v bat pd5 pd6 boot0 pd7 v ss _2 v ss a pa1 v dd_2 v dd_1 pb14 pa0-wkup 10 9 k j pd10 pd11 pa 8 pa9 pa10 pa11 pa12 pc10 pa1 3 pa14 pc9 pc7 pc6 pd15 pc 8 pd14 pe12 pb1 pa7 pb11 pe 8 pb0 pa6 pb10 pe1 3 pe9 v dda pb1 3 v ref+ pa 3 pb12 pa2 pd 8 pd9 pd1 3 pd12
pinouts and pin descriptions stm32f103xc, stm32f103xd, stm32f103xe 26/130 doc id 14611 rev 8 figure 5. stm32f103xc and stm32f103xe performance line lqfp144 pinout v dd_3 v ss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 v dd_11 v ss_11 pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 v dd_10 v ss_10 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 pe2 v dd_2 pe3 v ss_2 pe4 nc pe5 pa13 pe6 pa12 vbat pa11 pc13-tamper-rtc pa10 pc14-osc32_in pa9 pc15-osc32_out pa8 pf0 pc9 pf1 pc8 pf2 pc7 pf3 pc6 pf4 v dd_9 pf5 v ss_9 v ss_5 pg8 v dd_5 pg7 pf6 pg6 pf7 pg5 pf8 pg4 pf9 pg3 pf10 pg2 osc_in pd15 osc_out pd14 nrst v dd_8 pc0 v ss_8 pc1 pd13 pc2 pd12 pc3 pd11 v ssa pd10 v ref- pd9 v ref+ pd8 v dda pb15 pa0-wkup pb14 pa1 pb13 pa2 pb12 pa3 v ss_4 v dd_4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pf11 pf12 vss_6 v dd_6 pf13 pf14 pf15 pg0 pg1 pe7 pe8 pe9 v ss_7 v dd_7 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 v ss_1 v dd_1 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 lqfp144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai14667
stm32f103xc, stm32f103xd, stm32f103xe pinouts and pin descriptions doc id 14611 rev 8 27/130 figure 6. stm32f103xc and stm32f103xe performance line lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vdd_2 vss_2 nc pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pe2 pe3 pe4 pe5 pe6 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out vss_5 vdd_5 osc_in osc_out nrst pc0 pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p pa 1 pa 2 ai14391 lqfp100
pinouts and pin descriptions stm32f103xc, stm32f103xd, stm32f103xe 28/130 doc id 14611 rev 8 figure 7. stm32f103xc and stm32f103xe performance line lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out pd0 osc_in pd1 osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai14392
stm32f103xc, stm32f103xd, stm32f103xe pinouts and pin descriptions doc id 14611 rev 8 29/130 figure 8. stm32f103xc and stm32f103xe performance line wlcsp64 ballout, ball side ai15460b h d c b a 87654321 g f e v dd_2 pc10 pd2 pb5 pb3 boot0 v ss_3 v dd_3 bypass/ v ss_2 pa14 pc11 pb4 pb6 pb9 pc15 pc14 pc13 nrst v bat pb7 pc12 pa15 pa12 pa11 osc_in osc_out pc2 pb8 pa13 pa10 pa9 pc9 pc0 v ssa pa1 pa5 pa8 pc8 pc7 pc6 pc1 v ref+ pa0- wkup v ss_4 pb1 pb11 pb14 pb15 v dda pa3 v dd_4 pa6 pa7 pb10 pb12 pb13 pa2 pa4 pc4 pc5 pb0 pb2 v ss_1 v dd_1
pinouts and pin descriptions stm32f103xc, stm32f103xd, stm32f103xe 30/130 doc id 14611 rev 8 table 5. high-density stm32f103xx pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lfbga100 wlcsp64 lqfp64 lqfp100 lqfp144 default remap a3 a3 - - 1 1 pe2 i/o ft pe2 traceck/ fsmc_a23 a2 b3 - - 2 2 pe3 i/o ft pe3 traced0/fsmc_a19 b2 c3 - - 3 3 pe4 i/o ft pe4 traced1/fsmc_a20 b3 d3 - - 4 4 pe5 i/o ft pe5 traced2/fsmc_a21 b4 e3 - - 5 5 pe6 i/o ft pe6 traced3/fsmc_a22 c2 b2 c6 1 6 6 v bat sv bat a1 a2 c8 2 7 7 pc13-tamper- rtc (5) i/o pc13 (6) tamper-rtc b1 a1 b8 3 8 8 pc14- osc32_in (5) i/o pc14 (6) osc32_in c1 b1 b7 4 9 9 pc15- osc32_out (5) i/o pc15 (6) osc32_out c3 - - - - 10 pf0 i/o ft pf0 fsmc_a0 c4 - - - - 11 pf1 i/o ft pf1 fsmc_a1 d4 - - - - 12 pf2 i/o ft pf2 fsmc_a2 e2 - - - - 13 pf3 i/o ft pf3 fsmc_a3 e3 - - - - 14 pf4 i/o ft pf4 fsmc_a4 e4 - - - - 15 pf5 i/o ft pf5 fsmc_a5 d2 c2 - - 10 16 v ss_5 sv ss_5 d3 d2 - - 11 17 v dd_5 sv dd_5 f3 - - - - 18 pf6 i/o pf6 adc3_in4/fsmc_niord f2 - - - - 19 pf7 i/o pf7 adc3_in5/fsmc_nreg g3 - - - - 20 pf8 i/o pf8 adc3_in6/fsmc_niowr g2 - - - - 21 pf9 i/o pf9 adc3_in7/fsmc_cd g1 - - - - 22 pf10 i/o pf10 adc3_in8/fsmc_intr d1 c1 d8 5 12 23 osc_in i osc_in e1 d1 d7 6 13 24 osc_out o osc_out f1 e1 c7 7 14 25 nrst i/o nrst h1 f1 e8 8 15 26 pc0 i/o pc0 adc123_in10 h2 f2 f8 9 16 27 pc1 i/o pc1 adc123_in11 h3 e2 d6 10 17 28 pc2 i/o pc2 adc123_in12 h4 f3 - 11 18 29 pc3 i/o pc3 adc123_in13 j1 g1 e7 12 19 30 v ssa sv ssa
stm32f103xc, stm32f103xd, stm32f103xe pinouts and pin descriptions doc id 14611 rev 8 31/130 k1 h1 - - 20 31 v ref- sv ref- l1 j1 f7 (7) -2132 v ref+ sv ref+ m1 k1 g8 13 22 33 v dda sv dda j2 g2 f6 14 23 34 pa0-wkup i/o pa0 wkup/usart2_cts (8) adc123_in0 tim2_ch1_etr tim5_ch1/tim8_etr k2 h2 e6 15 24 35 pa1 i/o pa1 usart2_rts (8) adc123_in1/ tim5_ch2/tim2_ch2 (8) l2 j2 h8 16 25 36 pa2 i/o pa2 usart2_tx (8) /tim5_ch3 adc123_in2/ tim2_ch3 (8) m2 k2 g7 17 26 37 pa3 i/o pa3 usart2_rx (8) /tim5_ch4 adc123_in3/tim2_ch4 (8) g4 e4 f5 18 27 38 v ss_4 sv ss_4 f4 f4 g6 19 28 39 v dd_4 sv dd_4 j3 g3 h7 20 29 40 pa4 i/o pa4 spi1_nss (8) / usart2_ck (8) dac_out1/adc12_in4 k3 h3 e5 21 30 41 pa5 i/o pa5 spi1_sck (8) dac_out2 adc12_in5 l3 j3 g5 22 31 42 pa6 i/o pa6 spi1_miso (8) tim8_bkin/adc12_in6 tim3_ch1 (8) tim1_bkin m3 k3 g4 23 32 43 pa7 i/o pa7 spi1_mosi (8) / tim8_ch1n/adc12_in7 tim3_ch2 (8) tim1_ch1n j4 g4 h6 24 33 44 pc4 i/o pc4 adc12_in14 k4 h4 h5 25 34 45 pc5 i/o pc5 adc12_in15 l4 j4 h4 26 35 46 pb0 i/o pb0 adc12_in8/tim3_ch3 tim8_ch2n tim1_ch2n m4 k4 f4 27 36 47 pb1 i/o pb1 adc12_in9/tim3_ch4 (8) tim8_ch3n tim1_ch3n j5 g5 h3 28 37 48 pb2 i/o ft pb2/boot1 m5 - - - - 49 pf11 i/o ft pf11 fsmc_nios16 l5 - - - - 50 pf12 i/o ft pf12 fsmc_a6 table 5. high-density stm32f103 xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lfbga100 wlcsp64 lqfp64 lqfp100 lqfp144 default remap
pinouts and pin descriptions stm32f103xc, stm32f103xd, stm32f103xe 32/130 doc id 14611 rev 8 h5 - - - - 51 v ss_6 sv ss_6 g5 - - - - 52 v dd_6 sv dd_6 k5 - - - - 53 pf13 i/o ft pf13 fsmc_a7 m6 - - - - 54 pf14 i/o ft pf14 fsmc_a8 l6 - - - - 55 pf15 i/o ft pf15 fsmc_a9 k6 - - - - 56 pg0 i/o ft pg0 fsmc_a10 j6 - - - - 57 pg1 i/o ft pg1 fsmc_a11 m7 h5 - - 38 58 pe7 i/o ft pe7 fsmc_d4 tim1_etr l7 j5 - - 39 59 pe8 i/o ft pe8 fsmc_d5 tim1_ch1n k7 k5 - - 40 60 pe9 i/o ft pe9 fsmc_d6 tim1_ch1 h6 - - - - 61 v ss_7 sv ss_7 g6 - - - - 62 v dd_7 sv dd_7 j7 g6 - - 41 63 pe10 i/o ft pe10 fsmc_d7 tim1_ch2n h8 h6 - - 42 64 pe11 i/o ft pe11 fsmc_d8 tim1_ch2 j8 j6 - - 43 65 pe12 i/o ft pe12 fsmc_d9 tim1_ch3n k8 k6 - - 44 66 pe13 i/o ft pe13 fsmc_d10 tim1_ch3 l8 g7 - - 45 67 pe14 i/o ft pe14 fsmc_d11 tim1_ch4 m8 h7 - - 46 68 pe15 i/o ft pe15 fsmc_d12 tim1_bkin m9 j7 g3 29 47 69 pb10 i/o ft pb10 i2c2_scl/usart3_tx (8) tim2_ch3 m10 k7 f3 30 48 70 pb11 i/o ft pb11 i2c2_sda/usart3_rx (8) tim2_ch4 h7 e7 h2 31 49 71 v ss_1 sv ss_1 g7 f7 h1 32 50 72 v dd_1 sv dd_1 m11 k8 g2 33 51 73 pb12 i/o ft pb12 spi2_nss/i2s2_ws/ i2c2_smba/ usart3_ck (8) / tim1_bkin (8) m12 j8 g1 34 52 74 pb13 i/o ft pb13 spi2_sck/i2s2_ck usart3_cts (8) / tim1_ch1n l11 h8 f2 35 53 75 pb14 i/o ft pb14 spi2_miso/tim1_ch2n usart3_rts (8) / l12 g8 f1 36 54 76 pb15 i/o ft pb15 spi2_mosi/i2s2_sd tim1_ch3n (8) / l9 k9 - - 55 77 pd8 i/o ft pd8 fsmc_d13 usart3_tx k9 j9 - - 56 78 pd9 i/o ft pd9 fsmc_d14 usart3_rx table 5. high-density stm32f103 xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lfbga100 wlcsp64 lqfp64 lqfp100 lqfp144 default remap
stm32f103xc, stm32f103xd, stm32f103xe pinouts and pin descriptions doc id 14611 rev 8 33/130 j9 h9 - - 57 79 pd10 i/o ft pd10 fsmc_d15 usart3_ck h9 g9 - - 58 80 pd11 i/o ft pd11 fsmc_a16 usart3_cts l10 k10 - - 59 81 pd12 i/o ft pd12 fsmc_a17 tim4_ch1 / usart3_rts k10 j10 - - 60 82 pd13 i/o ft pd13 fsmc_a18 tim4_ch2 g8 - - - - 83 v ss_8 sv ss_8 f8 - - - - 84 v dd_8 sv dd_8 k11 h10 - - 61 85 pd14 i/o ft pd14 fsmc_d0 tim4_ch3 k12 g10 - - 62 86 pd15 i/o ft pd15 fsmc_d1 tim4_ch4 j12 - - - - 87 pg2 i/o ft pg2 fsmc_a12 j11 - - - - 88 pg3 i/o ft pg3 fsmc_a13 j10 - - - - 89 pg4 i/o ft pg4 fsmc_a14 h12 - - - - 90 pg5 i/o ft pg5 fsmc_a15 h11 - - - - 91 pg6 i/o ft pg6 fsmc_int2 h10 - - - - 92 pg7 i/o ft pg7 fsmc_int3 g11 - - - - 93 pg8 i/o ft pg8 g10 - - - - 94 v ss_9 sv ss_9 f10 - - - - 95 v dd_9 sv dd_9 g12 f10 e1 37 63 96 pc6 i/o ft pc6 i2s2_mck/ tim8_ch1/sdio_d6 tim3_ch1 f12 e10 e2 38 64 97 pc7 i/o ft pc7 i2s3_mck/ tim8_ch2/sdio_d7 tim3_ch2 f11 f9 e3 39 65 98 pc8 i/o ft pc8 tim8_ch3/sdio_d0 tim3_ch3 e11 e9 d1 40 66 99 pc9 i/o ft pc9 tim8_ch4/sdio_d1 tim3_ch4 e 1 2 d 9 e 4 4 1 6 7 1 0 0 pa 8 i / o f t pa 8 usart1_ck/ tim1_ch1 (8) /mco d 1 2 c 9 d 2 4 2 6 8 1 0 1 pa 9 i / o f t pa 9 usart1_tx (8) / tim1_ch2 (8) d11 d10 d3 43 69 102 pa10 i/o ft pa10 usart1_rx (8) / tim1_ch3 (8) c12 c10 c1 44 70 103 pa11 i/o ft pa11 usart1_cts/usbdm can_rx (8) /tim1_ch4 (8) b12 b10 c2 45 71 104 pa12 i/o ft pa12 usart1_rts/usbdp/ can_tx (8) /tim1_etr (8) table 5. high-density stm32f103 xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lfbga100 wlcsp64 lqfp64 lqfp100 lqfp144 default remap
pinouts and pin descriptions stm32f103xc, stm32f103xd, stm32f103xe 34/130 doc id 14611 rev 8 a12 a10 d4 46 72 105 pa13 i/o ft jtms- swdio pa 1 3 c11 f8 - - 73 106 not connected g9 e6 b1 47 74 107 v ss_2 sv ss_2 f9 f6 a1 48 75 108 v dd_2 sv dd_2 a11 a9 b2 49 76 109 pa14 i/o ft jtck- swclk pa 1 4 a10 a8 c3 50 77 110 pa15 i/o ft jtdi spi3_nss/ i2s3_ws tim2_ch1_etr pa 15 / spi1_nss b11 b9 a2 51 78 111 pc10 i/o ft pc10 uart4_tx/sdio_d2 usart3_tx b10 b8 b3 52 79 112 pc11 i/o ft pc11 uart4_rx/sdio_d3 usart3_rx c10 c8 c4 53 80 113 pc12 i/o ft pc1 2 uart5_tx/sdio_ck usart3_ck e10 d8 d8 5 81 114 pd0 i/o ft osc_in (9) fsmc_d2 (10) can_rx d10 e8 d7 6 82 115 pd1 i/o ft osc_out (9) fsmc_d3 (10) can_tx e9 b7 a3 54 83 116 pd2 i/o ft pd2 tim3_etr/uart5_rx sdio_cmd d9 c7 - - 84 117 pd3 i/o ft pd3 fsmc_clk usart2_cts c9 d7 - - 85 118 pd4 i/o ft pd4 fsmc_noe usart2_rts b9 b6 - - 86 119 pd5 i/o ft pd5 fsmc_nwe usart2_tx e7 - - - - 120 v ss_10 s v ss_10 f7 - - - - 121 v dd_10 s v dd_10 a8 c6 - - 87 122 pd6 i/o ft pd6 fsmc_nwait usart2_rx a9 d6 - - 88 123 pd7 i/o ft pd7 fsmc_ne1/fsmc_nce2 usart2_ck e8 - - - - 124 pg9 i/o ft pg9 fsmc_ne2/fsmc_nce3 d8 - - - - 125 pg10 i/o ft pg10 fsmc_nce4_1/ fsmc_ne3 c8 - - - - 126 pg11 i/o ft pg11 fsmc_nce4_2 b8 - - - - 127 pg12 i/o ft pg12 fsmc_ne4 d7 - - - - 128 pg13 i/o ft pg13 fsmc_a24 c7 - - - - 129 pg14 i/o ft pg14 fsmc_a25 e6 - - - - 130 v ss_11 sv ss_11 f6 - - - - 131 v dd_11 sv dd_11 b7 - - - - 132 pg15 i/o ft pg15 table 5. high-density stm32f103 xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lfbga100 wlcsp64 lqfp64 lqfp100 lqfp144 default remap
stm32f103xc, stm32f103xd, stm32f103xe pinouts and pin descriptions doc id 14611 rev 8 35/130 a7 a7 a4 55 89 133 pb3 i/o ft jtdo spi3_sck / i2s3_ck/ pb3 / traceswo tim2_ch2 / spi1_sck a6 a6 b4 56 90 134 pb4 i/o ft njtrst spi3_miso pb4 / tim3_ch1 spi1_miso b6 c5 a5 57 91 135 pb5 i/o pb5 i2c1_smba/ spi3_mosi i2s3_sd tim3_ch2 / spi1_mosi c6 b5 b5 58 92 136 pb6 i/o ft pb6 i2c1_scl (8) / tim4_ch1 (8) usart1_tx d6 a5 c5 59 93 137 pb7 i/o ft pb7 i2c1_sda (8) / fsmc_nadv / tim4_ch2 (8) usart1_rx d5 d5 a6 60 94 138 boot0 i boot0 c5 b4 d5 61 95 139 pb8 i/o ft pb8 tim4_ch3 (8) /sdio_d4 i2c1_scl/ can_rx b5 a4 b6 62 96 140 pb9 i/o ft pb9 tim4_ch4 (8) /sdio_d5 i2c1_sda / can_tx a5 d4 - - 97 141 pe0 i/o ft pe0 tim4_etr / fsmc_nbl0 a4 c4 - - 98 142 pe1 i/o ft pe1 fsmc_nbl1 e5 e5 a7 63 99 143 v ss_3 sv ss_3 f5 f5 a8 64 100 144 v dd_3 sv dd_3 1. i = input, o = output, s = supply. 2. ft = 5 v tolerant. 3. function availability depends on the chosen device. 4. if several peripherals share the same i/o pin, to avoid conflict between these al ternate functions only one peripheral should be enabled at a time through the peri pheral clock enable bit (in the correspondi ng rcc peripheral clock enable register). 5. pc13, pc14 and pc15 are supplied through the power switch. sinc e the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is li mited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these ios must not be used as a current source (e.g. to drive an led). 6. main function after the first backup domain power-up. later on, it depends on the contents of the backup registers even after reset (because these registers are not reset by the main reset). for details on how to manage these ios, refer to the battery backup domain and bkp register description sections in the stm32f10xxx reference manual, available from the stmicroelectronics website: www.st.com. 7. unlike in the lqfp64 package, there is no pc3 in the wlcsp package. the v ref+ functionality is provided instead. 8. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug conf iguration section in the st m32f10xxx reference manual, available from the stmicroel ectronics website: www.st.com. 9. for the lqfp64 package, the pins number 5 and 6 are c onfigured as osc_in/osc_out after reset, however the functionality of pd0 and pd1 can be remapped by software on these pins. for the lqfp100/bga100 and lqfp144/bga144 packages, pd0 and pd1 are available by default, so there is no need for remapping. for more details, refer to alternate function i/o and debug configurati on section in the stm32f10xxx reference manual. 10. for devices delivered in lq fp64 packages, the fsmc f unction is not available. table 5. high-density stm32f103 xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lfbga100 wlcsp64 lqfp64 lqfp100 lqfp144 default remap
pinouts and pin descriptions stm32f103xc, stm32f103xd, stm32f103xe 36/130 doc id 14611 rev 8 table 6. fsmc pin definition pins fsmc lqfp100 bga100 (1) cf cf/ide nor/psram/ sram nor/psram mux nand 16 bit pe2 a23 a23 yes pe3 a19 a19 yes pe4 a20 a20 yes pe5 a21 a21 yes pe6 a22 a22 yes pf0 a0 a0 a0 - pf1 a1 a1 a1 - pf2 a2 a2 a2 - pf3 a3 a3 - pf4 a4 a4 - pf5 a5 a5 - pf6 niord niord - pf7 nreg nreg - pf8 niowr niowr - pf9 cd cd - pf10 intr intr - pf11 nios16 nios16 - pf12 a6 a6 - pf13 a7 a7 - pf14 a8 a8 - pf15 a9 a9 - pg0 a10 a10 - pg1 a11 - pe7 d4 d4 d4 da4 d4 yes pe8 d5 d5 d5 da5 d5 yes pe9 d6 d6 d6 da6 d6 yes pe10 d7 d7 d7 da7 d7 yes pe11 d8 d8 d8 da8 d8 yes pe12 d9 d9 d9 da9 d9 yes pe13 d10 d10 d10 da10 d10 yes pe14 d11 d11 d11 da11 d11 yes pe15 d12 d12 d12 da12 d12 yes pd8 d13 d13 d13 da13 d13 yes
stm32f103xc, stm32f103xd, stm32f103xe pinouts and pin descriptions doc id 14611 rev 8 37/130 pd9 d14 d14 d14 da14 d14 yes pd10 d15 d15 d15 da15 d15 yes pd11 a16 a16 cle yes pd12 a17 a17 ale yes pd13 a18 a18 yes pd14 d0 d0 d0 da0 d0 yes pd15 d1 d1 d1 da1 d1 yes pg2 a12 - pg3 a13 - pg4 a14 - pg5 a15 - pg6 int2 - pg7 int3 - pd0 d2 d2 d2 da2 d2 yes pd1 d3 d3 d3 da3 d3 yes pd3 clk clk yes pd4 noe noe noe noe noe yes pd5 nwe nwe nwe nwe nwe yes pd6 nwait nwait nwait nwait nwait yes pd7 ne1 ne1 nce2 yes pg9 ne2 ne2 nce3 - pg10 nce4_1 nce4_1 ne3 ne3 - pg11 nce4_2 nce4_2 - pg12 ne4 ne4 - pg13 a24 a24 - pg14 a25 a25 - pb7 nadv nadv yes pe0 nbl0 nbl0 yes pe1 nbl1 nbl1 yes 1. ports f and g are not available in dev ices delivered in 100-pin packages. table 6. fsmc pin definition (continued) pins fsmc lqfp100 bga100 (1) cf cf/ide nor/psram/ sram nor/psram mux nand 16 bit
memory mapping stm32f103xc, stm32f103xd, stm32f103xe 38/130 doc id 14611 rev 8 4 memory mapping the memory map is shown in figure 9 . figure 9. memory map 512-mbyte block 7 cortex-m3's internal peripherals 512-mbyte block 6 not used 512-mbyte block 5 fsmc register 512-mbyte block 4 fsmc bank 3 & bank4 512-mbyte block 3 fsmc bank1 & bank2 512-mbyte block 2 peripherals 512-mbyte block 1 sram 0x0000 0000 0x1fff ffff 0x2000 0000 0x3fff ffff 0x4000 0000 0x5fff ffff 0x6000 0000 0x7fff ffff 0x8000 0000 0x9fff ffff 0xa000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xffff ffff 512-mbyte block 0 code flash 0x0808 0000 0x1fff efff 0x1fff f000- 0x1fff f7ff 0x1fff f800 - 0x1fff f80f 0x0800 0000 0x0807 ffff 0x0008 0000 0x07ff ffff 0x0000 0000 0x0007 ffff system memory reserved reserved aliased to flash or system memory depending on boot pins sram (64 kb aliased by bit-banding) reserved 0x2000 0000 0x2000 ffff 0x2001 0000 0x3fff ffff tim2 tim3 0x4000 0000 - 0x4000 03ff tim4 tim5 tim6 tim7 reserved 0x4000 0400 - 0x4000 07ff 0x4000 0800 - 0x4000 0bff 0x4000 0c00 - 0x4000 0fff 0x4000 1000 - 0x4000 13ff 0x4000 1400 - 0x4000 17ff 0x4000 1800 - 0x4000 27ff rtc 0x4000 2800 - 0x4000 2bff wwdg 0x4000 2c00 - 0x4000 2fff iwdg 0x4000 3000 - 0x4000 33ff reserved 0x4000 3400 - 0x4000 37ff spi2/i 2 s2 0x4000 3800 - 0x4000 3bff spi3/i 2 s3 0x4000 3c00 - 0x4000 3fff reserved 0x4000 4000 - 0x4000 43ff usart2 0x4000 4400 - 0x4000 47ff 0x4000 4800 - 0x4000 4bff usart3 uart4 0x4000 4c00 - 0x4000 4fff uart5 0x4000 5000 - 0x4000 53ff i2c1 0x4000 5400 - 0x4000 57ff i2c2 0x4000 5800 - 0x4000 5bff reserved 0x4000 6800 - 0x4000 6bff bkp 0x4000 6c00 - 0x4000 6fff pwr 0x4000 7000 - 0x4000 73ff dac 0x4000 7400 - 0x4000 77ff reserved 0x4000 7800 - 0x4000 ffff afio 0x4001 0000 - 0x4001 03ff port a exti 0x4001 0400 - 0x4001 07ff 0x4001 0800 - 0x4001 0bff port b 0x4001 0c00 - 0x4001 0fff port c 0x4001 1000 - 0x4001 13ff port d 0x4001 1400 - 0x4001 17ff port e 0x4001 1800 - 0x4001 1bff port f 0x4001 1c00 - 0x4001 1fff port g 0x4001 2000 - 0x4001 23ff adc1 0x4001 2400 - 0x4001 27ff 0x4001 2800 - 0x4001 2bff spi1 0x4001 3000 - 0x4001 33ff 0x4001 3400 - 0x4001 37ff usart1 0x4001 3800 - 0x4001 3bff reserved 0x4001 400 - 0x4001 7fff dma1 0x4002 0000 - 0x4002 03ff dma2 0x4002 0400 - 0x4002 07ff reserved 0x4002 0400 - 0x4002 0fff rcc 0x4002 1000 - 0x4002 13ff reserved 0x4002 1400 - 0x4002 1fff flash interface 0x4002 2000 - 0x4002 23ff reserved 0x4002 2400 - 0x4002 2fff crc 0x4002 3000 - 0x4002 33ff reserved 0x4002 4400 - 0x5fff ffff fsmc bank1 nor/psram 1 0x6000 0000 - 0x63ff ffff fsmc bank1 nor/psram 2 0x6400 0000 - 0x67ff ffff fsmc bank1 nor/psram 3 0x6800 0000 - 0x6bff ffff fsmc bank1 nor/psram 4 0x6c00 0000 - 0x6fff ffff fsmc bank2 nand (nand1) 0x7000 0000 - 0x7fff ffff fsmc bank3 nand (nand2) 0x8000 0000 - 0x8fff ffff fsmc bank4 pccard 0x9000 0000 - 0x9fff ffff fsmc register 0xa000 0000 - 0xa000 0fff reserved 0xa000 1000 - 0xbfff ffff ai14753d option bytes tim8 adc2 0x4001 8000 - 0x4001 83ff 0x4001 8400 - 0x4001 ffff sdio reserved adc3 0x4001 3c00 - 0x4001 3fff tim1 0x4001 2c00 - 0x4001 2fff usb registers shared usb/can sram 512 bytes bxcan 0x4000 5c00 - 0x4000 5fff 0x4000 6000 - 0x4000 63ff 0x4000 6400 - 0x4000 67ff
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 39/130 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 10. pin loading condition s figure 11. pin input voltage ai14141 c = 50 pf stm32f103xx pin ai14142 stm32f103xx pin v in
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 40/130 doc id 14611 rev 8 5.1.6 power supply scheme figure 12. power supply scheme caution: in figure 12 , the 4.7 f capacitor must be connected to v dd3 . 5.1.7 current con sumption measurement figure 13. current consumption measurement scheme ai 6 $$ !n alo g 2#s0,, 0o werswi tch 6 "!4 '0 )/ s /54 ). +ernellogic #05 $igital -emories "ackupcircuitry /3#+24# "ackupregisters 7ake uplogic n& ?& 6 2egulator 6 33 6 $$! 6 2%& 6 2%& 6 33! !$# $!# ,evelshifter )/ ,ogic 6 $$ n& ?& 6 2%& n& ?& 6 $$ ai14126 v bat v dd v dda i dd _v bat i dd
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 41/130 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 7: voltage characteristics , table 8: current characteristics , and table 9: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 7. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 8: current characteristics for the maximum allowed injected current values. input voltage on five volt tolerant pin v ss ? 0.3 v dd + 4.0 input voltage on any other pin v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins 50 mv |v ssx ? v ss | variations between all the different ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.12: absolute maximum ratings (electrical sensitivity) table 8. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin ? 25 i inj(pin) (2) 2. negative injection disturbs the analog per formance of the device. see note 3 below table 62 on page 105 . injected current on five volt tolerant pins (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in v dd while a negative injection is induced by v in electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 42/130 doc id 14611 rev 8 5.3 operating conditions 5.3.1 general operating conditions table 9. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 10. general operating conditions symbol parameter co nditions min max unit f hclk internal ahb clock frequency 0 72 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 72 v dd standard operating voltage 2 3.6 v v dda (1) 1. when the adc is used, refer to table 59: adc characteristics . analog operating voltage (adc not used) must be the same potential as v dd (2) 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and operation. 23.6 v analog operating voltage (adc used) 2.4 3.6 v bat backup operating voltage 1.8 3.6 v p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (3) 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 120 ). lqfp144 666 mw lqfp100 434 lqfp64 444 lfbga100 500 lfbga144 500 wlcsp64 400 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (4) 4. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 120 ). ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (4) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 43/130 5.3.2 operating conditions at power-up / power-down the parameters given in ta bl e 1 1 are derived from tests performed under the ambient temperature condition summarized in ta b l e 1 0 . table 11. operating conditions at power-up / power-down 5.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 1 2 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . symbol parameter conditions min max unit t vdd v dd rise time rate 0 s/v v dd fall time rate 20 table 12. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis 100 mv v por/pdr power on/power down reset threshold falling edge 1.8 (1) 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (2) pdr hysteresis 40 mv t rsttempo (2) 2. guaranteed by design, not tested in production. reset temporization 1 2.5 4.5 ms
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 44/130 doc id 14611 rev 8 5.3.4 embedded reference voltage the parameters given in ta bl e 1 3 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . 5.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 13: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except when explicitly mentioned the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above) prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /2, f pclk2 = f hclk the parameters given in ta bl e 1 4 , ta bl e 1 5 and ta bl e 1 6 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . table 13. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.20 1.26 v ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 5.1 17.1 (2) 2. guaranteed by design, not tested in production. s v rerint (2) internal reference voltage spread over the temperature range v dd = 3 v 10 mv 10 mv t coeff (2) temperature coefficient 100 ppm/c
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 45/130 table 14. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. based on characterization , not tested in production. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 69 70 ma 48 mhz 50 50.5 36 mhz 39 39.5 24 mhz 27 28 16 mhz 20 20.5 8 mhz 11 11.5 external clock (2) , all peripherals disabled 72 mhz 37 37.5 48 mhz 28 28.5 36 mhz 22 22.5 24 mhz 16.5 17 16 mhz 12.5 13 8 mhz 8 8 table 15. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max (1) 1. data based on characterization results, tested in production at v dd max, f hclk max. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 66 67 ma 48 mhz 43.5 45.5 36 mhz 33 35 24 mhz 23 24.5 16 mhz 16 18 8 mhz 9 10.5 external clock (2) , all peripherals disabled 72 mhz 33 33.5 48 mhz 23 23.5 36 mhz 18 18.5 24 mhz 13 13.5 16 mhz 10 10.5 8 mhz 6 6.5
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 46/130 doc id 14611 rev 8 figure 14. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled figure 15. typical current consumption in run mode versus frequency (at 3.6 v)- code with data processing running from ram, peripherals disabled 0 10 20 30 40 50 60 70 -45 25 70 85 105 temperature (c) consumption (ma) 8 mhz 16 mhz 24 mhz 36 mhz 48 mhz 72 mhz 0 5 10 15 20 25 30 35 -45 25 70 85 105 temperature (c) consumption (ma) 8 mhz 16 mhz 24 mhz 36 mhz 48 mhz 72 mhz
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 47/130 table 16. maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max, f hclk max with peripherals enabled. unit t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 45 46 ma 48 mhz 31 32 36 mhz 24 25 24 mhz 17 17.5 16 mhz 12.5 13 8 mhz 8 8 external clock (2) , all peripherals disabled 72 mhz 8.5 9 48 mhz 7 7.5 36 mhz 6 6.5 24 mhz 5 5.5 16 mhz 4.5 5 8 mhz 4 4
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 48/130 doc id 14611 rev 8 figure 16. typical current consumption on v bat with rtc on vs. temperature at different v bat values table 17. typical and maximum current consumptions in stop and standby modes symbol parameter conditions typ (1) max unit v dd /v bat = 2.0 v v dd /v bat = 2.4 v v dd /v bat = 3.3 v t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 34.5 35 379 1130 a regulator in low-power mode, low- speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 24.5 25 365 1110 supply current in standby mode low-speed internal rc oscillator and independent watchdog on 33.8-- low-speed internal rc oscillator on, independent watchdog off 2.8 3.6 - - low-speed internal rc oscillator and independent watchdog off, low-speed oscillator and rtc off 1.9 2.1 5 (2) 6.5 (2) i dd_vbat backup domain supply current low-speed oscillator and rtc on 1.05 1.1 1.4 2 (2) 2.3 (2) 1. typical values are measured at t a = 25 c. 2. based on characterization, not tested in production. 0 0.5 1 1.5 2 2.5 ?45 25 8 5105 temper a t u re (c) con su mption ( a) 1. 8 v 2 v 2.4 v 3 . 3 v 3 .6 v a i17 33 7
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 49/130 figure 17. typical current consumption in stop mode with regulator in run mode versus temperature at different v dd values 0 100 200 300 400 500 600 700 -45257085105 temperature (c) consumption (a) 2.4v 2.7v 3.0v 3.3v 3.6v # # # # #onsumption ! 4emperature?# 6 6 6 6 6 ai
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 50/130 doc id 14611 rev 8 figure 18. typical current consumption in stop mode with regulator in low-power mode versus temperature at different v dd values 0 100 200 300 400 500 600 700 -45257085105 temperature (c) consumption (a) 2.4v 2.7v 3.0v 3.3v 3.6v # # # # #onsumption ! 4emperature?# 6 6 6 6 6 ai
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 51/130 figure 19. typical current consumption in standby mode versus temperature at different v dd values 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 -45 25 70 85 105 temperature (c) consumption (a) 2.4v 2.7v 3.0v 3.3v 3.6v # # # # #onsumption ! 4emperature?# 6 6 6 6 6 ai
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 52/130 doc id 14611 rev 8 typical current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load). all peripherals are disabled except if it is explicitly mentioned. the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /4, f pclk 2 = f hclk /2, f adcclk = f pclk2 /4 table 18. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in run mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 51 30.5 ma 48 mhz 34.6 20.7 36 mhz 26.6 16.2 24 mhz 18.5 11.4 16 mhz 12.8 8.2 8 mhz 7.2 5 4 mhz 4.2 3.1 2 mhz 2.7 2.1 1 mhz 2 1.7 500 khz 1.6 1.4 125 khz 1.3 1.2 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 64 mhz 45 27 ma 48 mhz 34 20.1 36 mhz 26 15.6 24 mhz 17.9 10.8 16 mhz 12.2 7.6 8 mhz 6.6 4.4 4 mhz 3.6 2.5 2 mhz 2.1 1.5 1 mhz 1.4 1.1 500 khz 1 0.8 125 khz 0.7 0.6
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 53/130 table 19. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in sleep mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 29.5 6.4 ma 48 mhz 20 4.6 36 mhz 15.1 3.6 24 mhz 10.4 2.6 16 mhz 7.2 2 8 mhz 3.9 1.3 4 mhz 2.6 1.2 2 mhz 1.85 1.15 1 mhz 1.5 1.1 500 khz 1.3 1.05 125 khz 1.2 1.05 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 64 mhz 25.6 5.1 48 mhz 19.4 4 36 mhz 14.5 3 24 mhz 9.8 2 16 mhz 6.6 1.4 8 mhz 3.3 0.7 4 mhz 2 0.6 2 mhz 1.25 0.55 1 mhz 0.9 0.5 500 khz 0.7 0.45 125 khz 0.6 0.45
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 54/130 doc id 14611 rev 8 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 2 0 . the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature and v dd supply voltage conditions summarized in ta bl e 7 table 20. peripheral current consumption (1) peripheral typical consumption at 25 c unit apb1 tim2 1.2 ma tim3 1.2 tim4 1.2 tim5 1.2 tim6 0.4 tim7 0.4 spi2 0.2 spi3 0.2 usart2 0.4 usart3 0.4 uart4 0.5 uart5 0.6 i2c1 0.4 i2c2 0.4 usb 0.65 can 0.72 dac 0.72
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 55/130 5.3.6 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 2 1 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 1 0 . apb2 gpioa 0.55 ma gpiob 0.72 gpioc 0.72 gpiod 0.55 gpioe 1 gpiof 0.72 gpiog 1 adc1 (2) 1.9 adc2 1.7 tim1 1.8 spi1 0.4 tim8 1.7 usart1 0.9 adc3 1.7 1. f hclk = 72 mhz, f apb1 = f hclk /2, f apb2 = f hclk , default prescaler value for each peripheral. 2. specific conditions for adc: f hclk = 56 mhz, f apb1 = f hclk /2, f apb2 = f hclk , f adcclk = f apb2/4 , adon bit in the adc_cr2 register is set to 1. table 20. peripheral current consumption (1) (continued) peripheral typical consumption at 25 c unit table 21. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 1825mhz v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 5 ns t r(hse) t f(hse) osc_in rise or fall time (1) 20 c in(hse) osc_in input capacitance (1) 5pf ducy (hse) duty cycle 45 55 % i l osc_in input leakage current v ss v in v dd 1 a
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 56/130 doc id 14611 rev 8 low-speed external user clock generated from an external source the characteristics given in ta b l e 2 2 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 1 0 . figure 20. high-speed external clock source ac timing diagram table 22. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 ns t r(lse) t f(lse) osc32_in rise or fall time (1) 50 c in(lse) osc32_in input capacitance (1) 5pf ducy (lse) duty cycle 30 70 % i l osc32_in input leakage current v ss v in v d d 1 a ai14143 os c _i n exter nal stm32f103xx clo ck so urc e v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 57/130 figure 21. low-speed external clock source ac timing diagram ai14144b osc32_in exter nal stm32f103xx clo ck so urc e v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 58/130 doc id 14611 rev 8 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 16 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 3 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 22 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available fr om the st website www.st.com. figure 22. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. table 23. hse 4-16 mhz oscillator characteristics (1)(2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization results, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 8 16 mhz r f feedback resistor 200 k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 30 pf i 2 hse driving current v dd = 3.3 v, v in =v ss with 30 pf load 1ma g m oscillator transconductance startup 25 ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized 2 ms ai14145 osc_ou t osc_in f hse c l1 r f stm32f103xx 8 mh z resonator r ext (1) c l2 resonator with integrated capacitors bias controlled gain
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 59/130 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 4 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for c l1 and c l2 , it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 23 ). c l1 and c l2, are usually the same size. the crystal ma nufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. table 24. lse oscillator characteristics (f lse = 32.768 khz) (1) (2) symbol parameter conditions min typ max unit r f feedback resistor 5 m c l1 , c l2 recommended load capacitance versus equivalent serial resistance of the crystal (r s ) r s = 30 k 15 pf i 2 lse driving current v dd = 3.3 v, v in = v ss 1.4 a g m oscillator transconductance 5 a/v t su(lse) (3) startup time v dd is stabilized t a = 50 c 1.5 s t a = 25 c 2.5 t a = 10 c 4 t a = 0 c 6 t a = -10 c 10 t a = -20 c 17 t a = -30 c 32 t a = -40 c 60 1. based on characterization, not tested in production. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. t su(lse) is the startup time measured from the moment it is enab led (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly wi th the crystal manufacturer
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 60/130 doc id 14611 rev 8 figure 23. typical application with a 32.768 khz crystal 5.3.7 internal clock source characteristics the parameters given in ta bl e 2 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator ai14146 osc32_ou t osc32_in f lse c l1 r f stm32f103xx 32.768 kh z resonator c l2 resonator with integrated capacitors bias controlled gain table 25. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz ducy (hsi) duty cycle 45 55 % acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibration? available from the st website www.st.com. 1 (3) 3. guaranteed by design, not tested in production. % factory- calibrated (4) 4. based on characterization , not tested in production. t a = ?40 to 105 c ?2 2.5 % t a = ?10 to 85 c ?1.5 2.2 % t a = 0 to 70 c ?1.3 2 % t a = 25 c ?1.1 1.8 % t su(hsi) (4) hsi oscillator startup time 12s i dd(hsi) (4) hsi oscillator power consumption 80 100 a table 26. lsi oscillator characteristics (1) symbol parameter min typ max unit f lsi (2) frequency 30 40 60 khz
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 61/130 wakeup time from low-power mode the wakeup times given in ta b l e 2 7 is measured on a wakeup phase with a 8-mhz hsi rc oscillator. the clock source used to wake up the device depe nds from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 0 . t su(lsi) (3) lsi oscillator startup time 85 s i dd(lsi) (3) lsi oscillator power consumption 0.65 1.2 a 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. 2. based on characterization , not tested in production. 3. guaranteed by design, not tested in production. table 27. low-power mode wakeup timings symbol parameter typ unit t wusleep (1) 1. the wakeup times are measured from the wakeup even t to the point in which the user application code reads the first instruction. wakeup from sleep mode 1.8 s t wustop (1) wakeup from stop mode (regulator in run mode) 3.6 s wakeup from stop mode (regulator in low power mode) 5.4 t wustdby (1) wakeup from standby mode 50 s table 26. lsi oscillator characteristics (1) symbol parameter min typ max unit
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 62/130 doc id 14611 rev 8 5.3.8 pll characteristics the parameters given in ta bl e 2 8 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . 5.3.9 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. table 28. pll characteristics symbol parameter value unit min typ max (1) 1. based on characterization , not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 18.0 25 mhz pll input clock duty cycle 40 60 % f pll_out pll multiplier output clock 16 72 mhz t lock pll lock time 200 s jitter cycle-to-cycle jitter 300 ps table 29. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = ?40 to +105 c 40 52.5 70 s t erase page (2 kb) erase time t a = ?40 to +105 c 20 40 ms t me mass erase time t a = ?40 to +105 c 20 40 ms i dd supply current read mode f hclk = 72 mhz with 2 wait states, v dd = 3.3 v 28 ma write mode f hclk = 72 mhz, v dd = 3.3 v 7ma erase mode f hclk = 72 mhz, v dd = 3.3 v 5ma power-down mode / halt, v dd = 3.0 to 3.6 v 50 a v prog programming voltage 2 3.6 v
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 63/130 5.3.10 fsmc characteristics asynchronous waveforms and timings figure 24 through figure 27 represent asynchronous waveforms and ta b l e 3 1 through ta bl e 3 4 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: addresssetuptime = 0 addressholdtime = 1 datasetuptime = 1 table 30. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. based on characterization not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 64/130 doc id 14611 rev 8 figure 24. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 31. asynchronous non-multiplexed sram/psram/nor read timings (1) (2) symbol parameter min max unit t w(ne) fsmc_ne low time 5t hclk ? 1.5 5t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 0.5 1.5 ns t w(noe) fsmc_noe low time 5t hclk ? 1.5 5t hclk + 1.5 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time ?1.5 ns t v(a_ne) fsmc_nex low to fsmc_a valid 0 ns t h(a_noe) address hold time after fsmc_noe high 0.1 ns t v(bl_ne) fsmc_nex low to fsmc_bl valid 0 ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0 ns t su(data_ne) data to fsmc_nex high setup time 2t hclk + 25 ns t su(data_noe) data to fsmc_noex high setup time 2t hclk + 25 ns t h(data_noe) data hold time after fsmc_noe high 0 ns t h(data_ne) data hold time after fsmc_nex high 0 ns $ata &3-#?.% &3-#?.",;= &3-#?$;= t v",?.% t h$ata?.% &3-#?./% !ddress &3-#?!;= t v!?.% &3-#?.7% t su$ata?.% t w.% -36 w./% t t v./%?.% t h.%?./% t h$ata?./% t h!?./% t h",?./% t su$ata?./% &3-#?.!$6 t v.!$6?.% t w.!$6
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 65/130 figure 25. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. t v(nadv_ne) fsmc_nex low to fsmc_nadv low 5 ns t w(nadv) fsmc_nadv low time t hclk + 1.5 ns 1. c l = 15 pf. 2. based on characterisation , not tested in production. table 32. asynchronous non-multiplexed sram/psram/nor write timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk ? 1 3t hclk + 2 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk ? 0.5 t hclk + 1.5 ns t w(nwe) fsmc_nwe low time t hclk ? 0.5 t hclk + 1.5 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ns t v(a_ne) fsmc_nex low to fsmc_a valid 7.5 ns t h(a_nwe) address hold time after fsmc_nwe high t hclk ns t v(bl_ne) fsmc_nex low to fsmc_bl valid 1.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 0.5 ns t v(data_ne) fsmc_nex low to data valid t hclk + 7 ns t h(data_nwe) data hold time afte r fsmc_nwe high t hclk ns table 31. asynchronous non-multiplexed sram/psram/nor read timings (1) (2) symbol parameter min max unit nbl data fsmc_nex fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:0] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(data_ne) t w(ne) ai14990 fsmc_nadv (1) t v(nadv_ne) t w(nadv)
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 66/130 doc id 14611 rev 8 figure 26. asynchronous multiplexed psram/nor read waveforms t v(nadv_ne) fsmc_nex low to fsmc_nadv low 5.5 ns t w(nadv) fsmc_nadv low time t hclk + 1.5 ns 1. c l = 15 pf. 2. based on characterisation , not tested in production. table 33. asynchronous multiplexed psram/nor read timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 7t hclk ? 2 7t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 3t hclk ? 0.5 3t hclk + 1.5 ns t w(noe) fsmc_noe low time 4t hclk ? 1 4t hclk + 2 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time ?1 ns t v(a_ne) fsmc_nex low to fsmc_a valid 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 3 5 ns t w(nadv) fsmc_nadv low time t hclk ?1.5 t hclk + 1.5 ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high t hclk ns t h(a_noe) address hold time after fsmc_noe high t hclk ns table 32. asynchronous non-multiplexed sram/psram/nor write timings (1)(2) symbol parameter min max unit nbl data fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_ne) address fsmc_a[25:16] t v(a_ne) fsmc_nwe t v(a_ne) ai14892b address fsmc_nadv t v(nadv_ne) t w(nadv) t su(data_ne) t h(ad_nadv) fsmc_ne fsmc_noe t w(ne) t w(noe) t v(noe_ne) t h(ne_noe) t h(a_noe) t h(bl_noe) t su(data_noe) t h(data_noe)
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 67/130 t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0 ns t v(bl_ne) fsmc_nex low to fsmc_bl valid 0 ns t su(data_ne) data to fsmc_nex high setup time 2t hclk + 24 ns t su(data_noe) data to fsmc_noe high setup time 2t hclk + 25 ns t h(data_ne) data hold time after fsmc_nex high 0 ns t h(data_noe) data hold time after fsmc_noe high 0 ns 1. c l = 15 pf. 2. based on characterization , not tested in production. table 33. asynchronous multiplexed psram/nor read timings (1)(2) (continued) symbol parameter min max unit
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 68/130 doc id 14611 rev 8 figure 27. asynchronous multiplexed psram/nor write waveforms table 34. asynchronous multiplexed psram/nor write timings (1)(2) 1. c l = 15 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 5t hclk ? 1 5t hclk + 2 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low 2t hclk 2t hclk + 1 ns t w(nwe) fsmc_nwe low time 2t hclk ? 1 2t hclk + 2 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ? 1 ns t v(a_ne) fsmc_nex low to fsmc_a valid 7 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 3 5 ns t w(nadv) fsmc_nadv low time t hclk ? 1 t hclk + 1 ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high t hclk ? 3 ns t h(a_nwe) address hold time after fsmc_nwe high 4t hclk ns t v(bl_ne) fsmc_nex low to fsmc_bl valid 1.6 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1.5 ns t v(data_nadv) fsmc_nadv high to data valid t hclk + 1.5 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk ? 5 ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14891b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv)
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 69/130 synchronous waveforms and timings figure 28 through figure 31 represent synchronous waveforms and ta bl e 3 6 through ta bl e 3 8 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: burstaccessmode = fsmc_burstaccessmode_enable; memorytype = fsmc_memorytype_cram; writeburst = fsmc_writeburst_enable; clkdivision = 1; (0 is not supported, see the stm32f10xxx reference manual) datalatency = 1 for nor flash; datalatency = 0 for psram figure 28. synchronous multiplexed nor/psram read timings &3-#?#,+ &3-#?.%x &3-#?.!$6 &3-#?!;= &3-#?./% &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+, !)6 t d#,+, ./%, t d#,+, ./%( t d#,+, !$6 t d#,+, !$)6 t su!$6 #,+( t h#,+( !$6 t su!$6 #,+( t h#,+( !$6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 aih $
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 70/130 doc id 14611 rev 8 table 35. synchronous multiplexed nor/psram read timings (1)(2) 1. c l = 15 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 27.7 ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) 1.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low 4 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 5 ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 2 ns t d(clkl-noel) fsmc_clk low to fsmc_noe low 1 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 0.5 ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid 12 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high 6 ns t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high 0 ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 8 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 71/130 figure 29. synchronous multiplexed psram write timings &3-#?#,+ &3-#?.%x &3-#?.!$6 &3-#?!;= &3-#?.7% &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, .",( t d#,+, !$6 t d#,+, !$)6 t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aig t d#,+, $ata &3-#?.",
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 72/130 doc id 14611 rev 8 table 36. synchronous multiplexed psram write timings (1)(2) 1. c l = 15 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 27.7 ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) 2 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low 4 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 5 ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 2 ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1 ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid 12 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 3 ns t d(clkl-data) fsmc_a/d[15:0] valid after fsmc_clk low 6 ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 1 ns
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 73/130 figure 30. synchronous non-multiplexed nor/psram read timings table 37. synchronous non-multiplexed nor/psram read timings (1)(2) 1. c l = 15 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 27.7 ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) 1.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low 4 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 5 ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 0...25) 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 0...25) 4 ns t d(clkl-noel) fsmc_clk low to fsmc_noe low 1.5 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1.5 ns t su(dv-clkh) fsmc_d[15:0] valid data bef ore fsmc_clk high 6.5 ns t h(clkh-dv) fsmc_d[15:0] valid data after fsmc_clk high 7 ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_smclk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?./% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+, ./%, t d#,+, ./%( t su$6 #,+( t h#,+( $6 t su$6 #,+( t h#,+( $6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 aig &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( $
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 74/130 doc id 14611 rev 8 figure 31. synchronous non-multiplexed psram write timings table 38. synchronous non-multiplexed psram write timings (1)(2) 1. c l = 15 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 27.7 ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) 2 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low 4 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 5 ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 2 ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1 ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low 6 ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 1 ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?.7% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aih &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( t d#,+, $ata &3-#?.", t d#,+, .",(
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 75/130 pc card/compactflash controller waveforms and timings figure 32 through figure 37 represent synchronous waveforms and ta bl e 3 9 provides the corresponding timings. the results shown in th is table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x04; com.fsmc_waitsetuptime = 0x07; com.fsmc_holdsetuptime = 0x04; com.fsmc_hizsetuptime = 0x00; att.fsmc_setuptime = 0x04; att.fsmc_waitsetuptime = 0x07; att.fsmc_holdsetuptime = 0x04; att.fsmc_hizsetuptime = 0x00; io.fsmc_setuptime = 0x04; io.fsmc_waitsetuptime = 0x07; io.fsmc_holdsetuptime = 0x04; io.fsmc_hizsetuptime = 0x00; tclrsetuptime = 0; tarsetuptime = 0; figure 32. pc card/compactflash controller waveforms for common memory read access 1. fsmc_nce4_2 remains high (inactive during 8-bit access. fsmc_nwe t w(noe) fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 (1) fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nce4_1-noe) t su(d-noe) t h(noe-d) t v(ncex-a) t d(nreg-ncex) t d(niord-ncex) t h(ncex-ai) t h(ncex-nreg) t h(ncex-niord) t h(ncex- niowr ) ai14895b
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 76/130 doc id 14611 rev 8 figure 33. pc card/compactflash controller waveforms for common memory write access t d(nce4_1-nwe) t w(nwe) t h(nwe-d) t v(nce4_1-a) t d(nreg-nce4_1) t d(niord-nce4_1) t h(nce4_1-ai) memxhiz =1 t v(nwe-d) t h(nce4_1-nreg) t h(nce4_1-niord) t h(nce4_1-niowr) ai14896b fsmc_nwe fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) t d(d-nwe) fsmc_nce4_2 high
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 77/130 figure 34. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). t d(nce4_1-noe) t w(noe) t su(d-noe) t h(noe-d) t v(nce4_1-a) t h(nce4_1-ai) t d(nreg-nce4_1) t h(nce4_1-nreg) ai14897b fsmc_nwe fsmc_noe fsmc_d[15:0] (1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(noe-nce4_1) high
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 78/130 doc id 14611 rev 8 figure 35. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hiz). figure 36. pc card/compactflash controller waveforms for i/o space read access t w(nwe) t v(nce4_1-a) t d(nreg-nce4_1) t h(nce4_1-ai) t h(nce4_1-nreg) t v(nwe-d) ai14898b fsmc_nwe fsmc_noe fsmc_d[7:0](1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) high t d(nce4_1-nwe) t d(niord-nce4_1) t w(niord) t su(d-niord) t d(niord-d) t v(ncex-a) t h(nce4_1-ai) ai14899b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 79/130 figure 37. pc card/compactflash controller waveforms for i/o space write access t d(nce4_1-niowr) t w(niowr) t v(ncex-a) t h(nce4_1-ai) t h(niowr-d) attxhiz =1 t v(niowr-d) ai14900b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_niowr fsmc_nreg fsmc_niowr fsmc_niord table 39. switching characteristics for pc card/cf read and write cycles (1)(2) symbol parameter min max unit t v(ncex-a) t v(nce4_1-a) fsmc_ncex low (x = 4_1/4_2) to fsmc_ay valid (y = 0...10) fsmc_nce4_1 low (x = 4_1/4_2) to fsmc_ay valid (y = 0...10) 0 ns t h(ncex-ai) t h(nce4_1-ai) fsmc_ncex high (x = 4_1/4_2) to fsmc_ax invalid (x = 0...10) fsmc_nce4_1 high (x = 4_1/4_2) to fsmc_ax invalid (x = 0...10) 2.5 ns t d(nreg-ncex) t d(nreg-nce4_1) fsmc_ncex low to fsmc_nreg valid fsmc_nce4_1 low to fsmc_nreg valid 5 ns t h(ncex-nreg) t h(nce4_1-nreg) fsmc_ncex high to fsmc_nreg invalid fsmc_nce4_1 high to fsmc_nreg invalid t hclk + 3 ns t d(nce4_1-noe) fsmc_nce4_1 low to fsmc_noe low 5t hclk + 2 ns t w(noe) fsmc_noe low width 8t hclk ?1.5 8t hclk + 1 ns t d(noe-nce4_1 fsmc_noe high to fsmc_nce4_1 high 5t hclk + 2 ns t su(d-noe) fsmc_d[15:0] valid data before fsmc_noe high 25 ns t h(noe-d) fsmc_d[15:0] valid data after fsmc_noe high 15 ns t w(nwe) fsmc_nwe low width 8t hclk ? 1 8t hclk + 2 ns t d(nwe-nce4_1) fsmc_nwe high to fsmc_nce4_1 high 5t hclk + 2 ns t d(nce4_1-nwe) fsmc_nce4_1 low to fsmc_nwe low 5t hclk + 1.5 ns t v(nwe-d) fsmc_nwe low to fsmc_d[15:0] valid 0 ns t h(nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 11t hclk ns t d(d-nwe) fsmc_d[15:0] valid before fsmc_nwe high 13t hclk ns
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 80/130 doc id 14611 rev 8 nand controller waveforms and timings figure 38 through figure 41 represent synchronous waveforms and ta bl e 4 0 provides the corresponding timings. the results shown in th is table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x01; com.fsmc_waitsetuptime = 0x03; com.fsmc_holdsetuptime = 0x02; com.fsmc_hizsetuptime = 0x01; att.fsmc_setuptime = 0x01; att.fsmc_waitsetuptime = 0x03; att.fsmc_holdsetuptime = 0x02; att.fsmc_hizsetuptime = 0x01; bank = fsmc_bank_nand; memorydatawidth = fsmc_memorydatawidth_16b; ecc = fsmc_ecc_enable; eccpagesize = fsmc_eccpagesize_512bytes; tclrsetuptime = 0; tarsetuptime = 0; t w(niowr) fsmc_niowr low width 8t hclk + 3 ns t v(niowr-d) fsmc_niowr low to fsmc_d[15:0] valid 5t hclk +1 ns t h(niowr-d) fsmc_niowr high to fsmc_d[15:0] invalid 11t hclk ns t d(nce4_1-niowr) fsmc_nce4_1 low to fsmc_niowr valid 5t hclk +3ns ns t h(ncex-niowr) t h(nce4_1-niowr) fsmc_ncex high to fsmc_niowr invalid fsmc_nce4_1 high to fsmc_niowr invalid 5t hclk ? 5 ns t d(niord-ncex) t d(niord-nce4_1) fsmc_ncex low to fsmc_niord valid fsmc_nce4_1 low to fsmc_niord valid 5t hclk + 2.5 ns t h(ncex-niord) t h(nce4_1-niord) fsmc_ncex high to fsmc_niord invalid fsmc_nce4_1 high to fsmc_niord invalid 5t hclk ? 5 ns t su(d-niord) fsmc_d[15:0] valid before fsmc_niord high 4.5 ns t d(niord-d) fsmc_d[15:0] valid after fsmc_niord high 9 ns t w(niord) fsmc_niord low width 8t hclk + 2 ns 1. c l = 15 pf. 2. based on characterization, not tested in production. table 39. switching characteristics for pc card/cf read and write cycles (1)(2) (continued) symbol parameter min max unit
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 81/130 figure 38. nand controller waveforms for read access figure 39. nand controller waveforms for write access figure 40. nand controller waveforms for common memo ry read access fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] t su(d-noe) t h(noe-d) ai14901b ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-noe) t h(noe-ale) t h(nwe-d) t v(nwe-d) ai14902b fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-nwe) t h(nwe-ale) fsmc_nwe fsmc_n oe fsmc_d[15:0] t w(noe) t su(d-noe) t h(noe-d) ai14912b ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-noe) t h(noe-ale)
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 82/130 doc id 14611 rev 8 figure 41. nand controller waveforms for common memory write access table 40. switching characteristics fo r nand flash read and write cycles (1) 1. c l = 15 pf. symbol parameter min max unit t d(d-nwe) (2) 2. based on characterization , not tested in production. fsmc_d[15:0] valid before fsmc_nwe high 5t hclk + 12 ns t w(noe) (2) fsmc_noe low width 4t hclk ? 1.5 4t hclk + 1.5 ns t su(d-noe) (2) fsmc_d[15:0] valid data before fsmc_noe high 25 ns t h(noe-d) (2) fsmc_d[15:0] valid data after fsmc_noe high 7 ns t w(nwe) (2) fsmc_nwe low width 4t hclk ? 1 4t hclk + 2.5 ns t v(nwe-d) (2) fsmc_nwe low to fsmc_d[15:0] valid 0 ns t h(nwe-d) (2) fsmc_nwe high to fsmc_d[15:0] invalid 2t hclk + 4ns ns t d(ale-nwe) (3) 3. guaranteed by design, not tested in production. fsmc_ale valid before fsmc_nwe low 3t hclk + 1.5 ns t h(nwe-ale) (3) fsmc_nwe high to fsmc_ale invalid 3t hclk + 4.5 ns t d(ale-noe) (3) fsmc_ale valid before fsmc_noe low 3t hclk + 2 ns t h(noe-ale) (3) fsmc_nwe high to fsmc_ale invalid 3t hclk + 4.5 ns t w(nwe) t h(nwe-d) t v(nwe-d) ai14913b fsmc_nwe fsmc_n oe fsmc_d[15:0] t d(d-nwe) ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-nwe) t h(nwe-ale)
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 83/130 5.3.11 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 4 1 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) table 41. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25 c, f hclk = 72 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25 c, f hclk = 72 mhz conforms to iec 61000-4-4 4a
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 84/130 doc id 14611 rev 8 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 5.3.12 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 42. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz 8/72 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp144 package compliant with iec 61967-2 0.1 to 30 mhz 8 12 dbv 30 to 130 mhz 31 21 130 mhz to 1ghz 28 33 sae emi level 4 4 - table 43. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to jesd22-c101 ii 500
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 85/130 static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 5.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). the test results are given in ta b l e 4 5 table 44. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 45. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on osc_in32, osc_out32, pa4, pa5, pc13 -0 +0 ma injected current on all ft pins -5 +0 injected current on any other pin -5 +5
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 86/130 doc id 14611 rev 8 5.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 4 6 are derived from tests performed under the conditions summarized in ta b l e 1 0 . all i/os are cmos and ttl compliant. all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 42 and figure 43 for standard i/os, and in figure 44 and figure 45 for 5 v tolerant i/os. table 46. i/o static characteristics symbol parameter conditions min typ max unit v il standard io input low level voltage ?0.3 0.28*(v dd -2 v)+0.8 v v io ft (1) input low level voltage ?0.3 0.32*(v dd -2 v)+0.75 v v v ih standard io input high level voltage 0.41*(v dd -2 v)+1.3 v v dd +0.3 v io ft (1) input high level voltage v dd > 2 v 0.42*(v dd -2 v)+1 v 5.5 v v dd 2 v 5.2 v hys standard io schmitt trigger voltage hysteresis (2) 200 mv io ft schmitt trigger voltage hysteresis (2) 5% v dd (3) mv i lkg input leakage current (4) v ss v in v dd standard i/os 1 a v in = 5 v, i/o ft 3 r pu weak pull-up equivalent resistor (5) v in = v ss 30 40 50 k r pd weak pull-down equivalent resistor (5) v in = v dd 30 40 50 k c io i/o pin capacitance 5 pf 1. ft = five-volt tolerant. in order to sustain a voltage higher than v dd +0.3 the internal pull-up/pull-down resistors must be disabled. 2. hysteresis voltage between schmitt trigger switching levels. based on characteriza tion, not tested in production. 3. with a minimum of 100 mv. 4. leakage could be higher than max. if negativ e current is injected on adjacent pins. 5. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) .
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 87/130 figure 42. standard i/o input characteristics - cmos port figure 43. standard i/o input characteristics - ttl port aib 6 $$ 6 )nputrange notguaranteed 6 )( 6 $$ #-/3standardrequirement6 )( 6 $$ 6 )( 6 ), 6 #-/3standardrequirement6 ), 6 $$ 7 ),max 7 )(min 6 $$ 6 ), ai )nputrange notguaranteed 6 )( 6 ), 6 44,requirements 6 )( 6 6 )( 6 $$ 6 ), 6 $$ 44,requirements 6 ), 6 6 $$ 6 7 ),max 7 )(min
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 88/130 doc id 14611 rev 8 figure 44. 5 v tolerant i/o input characteristics - cmos port figure 45. 5 v tolerant i/o input characteristics - ttl port output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 8 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 8 ). 6$$ #-/3standardrequirements6 )( 6 $$ #-/3standardrequirment6 ), 6 $$ 6 )( 6 ), 6 6 $$ 6 )nputrange notguaranteed aib 6 )( 6 $$ 6 ), 6 $$ notguaranteed )nputrange 44,requirement6 )( 6 6 )(
6 $$ 6 ),
6 $$ 44,requirements6 ), 6 6 )( 6 ), 6 6 $$ 6 7 ),max 7 )(min ai
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 89/130 output voltage levels unless otherwise specified, the parameters given in ta bl e 4 7 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 0 . all i/os are cmos and ttl compliant. table 47. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 8 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time cmos port (2) i io = +8 ma 2.7 v < v dd < 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 8 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at same time ttl port (2) i io =+ 8ma 2.7 v < v dd < 3.6 v 0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 v ol (1)(4) 4. based on characterization data, not tested in production. output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v 1.3 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 v ol (1)(4) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v 0.4 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 90/130 doc id 14611 rev 8 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 46 and ta bl e 4 8 , respectively. unless otherwise specified, the parameters given in ta bl e 4 8 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 0 . table 48. i/o ac characteristics (1) 1. the i/o speed is configured using the modex[1:0] bi ts. refer to the stm32f10xxx reference manual for a description of gpio port configuration register. modex[1:0] bit value (1) symbol parameter conditions min max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 46 . c l = 50 pf, v dd = 2 v to 3.6 v 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) 3. guaranteed by design, not tested in production. ns t r(io)out output low to high level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to high level rise time 25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 ns
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 91/130 figure 46. i/o ac characteristics definition 5.3.15 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 4 6 ). unless otherwise specified, the parameters given in ta bl e 4 9 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 0 . figure 47. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 49 . otherwise the reset will not be taken into account by the device. ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50pf t t r(io)out table 49. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 0.8 v v ih(nrst) (1) nrst input high level voltage 2 v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse 100 ns v nf(nrst) (1) nrst input not filtered pulse 300 ns a i141 3 2d s tm 3 2f10xxx r pu nr s t (2) v dd filter intern a l re s et 0.1 f extern a l re s et circ u it (1)
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 92/130 doc id 14611 rev 8 5.3.16 tim time r characteristics the parameters given in ta bl e 5 0 are guaranteed by design. refer to section 5.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 50. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1 t timxclk f timxclk = 72 mhz 13.9 ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 72 mhz 0 36 mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk f timxclk = 72 mhz 0.0139 910 s t max_count maximum possible count 65536 65536 t timxclk f timxclk = 72 mhz 59.6 s
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 93/130 5.3.17 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 5 1 are derived from tests performed under ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta b l e 1 0 . the stm32f103xc, stm32f103xd and stm32f103xestm32f103xf and stm32f103xg performance line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 5 1 . refer also to section 5.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 51. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be higher than 2 mhz to achieve standard mode i 2 c frequencies. it must be higher than 4 mhz to achieve the fast mode i 2 c frequencies and it must be a multiple of 10 mhz in order to reach the i2c fast mode maximum clock speed of 400 khz. unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 0 (4) 4. the device must internally provide a hold time of at least 300ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 94/130 doc id 14611 rev 8 figure 48. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14149c start sd a 100 4.7k i 2 c bus 4.7k 100 v dd v dd stm32f103xx sda scl t f(sda) t r(sda) scl t h(sta) t w(sclh) t w(scll) t su(sda) t r(scl) t f(scl) t h(sda) s tart repeated start t su(sta) t su(sto) s top t w(sto:sta) table 52. scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed. 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x801e 300 0x8028 200 0x803c 100 0x00b4 50 0x0168 20 0x0384
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 95/130 i 2 s - spi characteristics unless otherwise specified, the parameters given in ta bl e 5 3 for spi or in ta bl e 5 4 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 1 0 . refer to section 5.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 53. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 18 mhz slave mode 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) 1. based on characterization , not tested in production. nss setup time slave mode 4t pclk ns t h(nss) (1) nss hold time slave mode 2t pclk t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 50 60 t su(mi) (1) t su(si) (1) data input setup time master mode 5 slave mode 5 t h(mi) (1) data input hold time master mode 5 t h(si) (1) slave mode 4 t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 20 mhz 0 3t pclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (1) data output valid time slave mode (after enable edge) 25 t v(mo) (1) data output valid time master mode (after enable edge) 5 t h(so) (1) data output hold time slave mode (after enable edge) 15 t h(mo) (1) master mode (after enable edge) 2
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 96/130 doc id 14611 rev 8 figure 49. spi timing diagram - slave mode and cpha = 0 figure 50. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 97/130 figure 51. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 98/130 doc id 14611 rev 8 table 54. i 2 s characteristics symbol parameter conditions min max unit ducy(sck) i2s slave input clock duty cycle slave mode 30 70 % f ck 1/t c(ck) i 2 s clock frequency master mode (data: 16 bits, audio frequency = 48 khz) 1.522 1.525 mhz slave mode 0 6.5 t r(ck) t f(ck) i 2 s clock rise and fall time capacitive load c l =50pf 8 ns t v(ws) (1) ws valid time master mode 3 t h(ws) (1) ws hold time master mode i2s2 2 i2s3 0 t su(ws) (1) ws setup time slave mode 4 t h(ws) (1) ws hold time slave mode 0 t w(ckh) (1) ck high and low time master f pclk = 16 mhz, audio frequency = 48 khz 312.5 t w(ckl) (1) 345 t su(sd_mr) (1) data input setup time master receiver i2s2 2 i2s3 6.5 t su(sd_sr) (1) data input setup time slave receiver 1.5 t h(sd_mr) (1)(2) data input hold time master receiver 0 t h(sd_sr) (1)(2) slave receiver 0.5 t v(sd_st) (1)(2) data output valid time slave transmitter (after enable edge) 18 t h(sd_st) (1) data output hold time slave transmitter (after enable edge) 11 t v(sd_mt) (1)(2) data output valid time master transmitter (after enable edge) 3 t h(sd_mt) (1) data output hold time master transmitter (after enable edge) 0 1. based on design simulation and/or characte rization results, not tested in production. 2. depends on f pclk . for example, if f pclk =8 mhz, then t pclk = 1/f plclk =125 ns.
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 99/130 figure 52. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 53. i 2 s master timing diagram (philips protocol) (1) 1. based on characterization , not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2)
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 100/130 doc id 14611 rev 8 sd/sdio mmc card host interface (sdio) characteristics unless otherwise specified, the parameters given in ta bl e 5 5 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta b l e 1 0 . refer to section 5.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (d[7:0], cmd, ck). figure 54. sdio high-speed mode figure 55. sd default mode t w(ckh) ck d, cmd (output) d, cmd (input) t c t w(ckl) t ov t oh t isu t ih t f t r ai14887 ck d, cmd (output) t ovd t ohd ai14888
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 101/130 usb characteristics the usb interface is usb-if certified (full speed). table 55. sd / mmc characteristics symbol parameter conditions min max unit f pp clock frequency in data transfer mode c l 30 pf 0 48 mhz t w(ckl) clock low time, f pp = 16 mhz c l 30 pf 32 ns t w(ckh) clock high time, f pp = 16 mhz c l 30 pf 31 t r clock rise time c l 30 pf 3.5 t f clock fall time c l 30 pf 5 cmd, d inputs (referenced to ck) t isu input setup time c l 30 pf 2 ns t ih input hold time c l 30 pf 0 cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time c l 30 pf 6 ns t oh output hold time c l 30 pf 0.3 cmd, d outputs (referenced to ck) in sd default mode (1) 1. refer to sdio_clkcr, the sdi clock control register to control the ck output. t ovd output valid default time c l 30 pf 7 ns t ohd output hold default time c l 30 pf 0.5 table 56. usb startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb transceiver startup time 1 s
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 102/130 doc id 14611 rev 8 figure 56. usb timings: definition of data signal rise and fall time 5.3.18 can (controller area network) interface refer to section 5.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). table 57. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 fu ll-speed electrical specification, the usbdp (d+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 v voltage range. 3.0 (3) 3. the stm32f103xx usb functionality is ensured dow n to 2.7 v but not the full usb electrical characteristics which are degr aded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (4) 4. guaranteed by characterizati on, not tested in production. differential input sensitivity i(usbdp, usbdm) 0.2 v v cm (4) differential common mode range includes v di range 0.8 2.5 v se (4) single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (5) 5. r l is the load connected on the usb drivers 0.3 v v oh static output level high r l of 15 k to v ss (5) 2.8 3.6 table 58. usb: full-speed electrical characteristics driver characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v ai14137 t f differen tial data lines v ss v cr s t r crossover points
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 103/130 5.3.19 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 5 9 are preliminary values derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 1 0 . note: it is recommended to perform a calibration after each power-up. table 59. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 3.6 v v ref+ positive reference voltage 2.4 v dda v i vref current on the v ref input pin 160 (1) 220 a f adc adc clock frequency 0.6 14 mhz f s (2) sampling rate 0.05 1 mhz f trig (2) external trigger frequency f adc = 14 mhz 823 khz 17 1/f adc v ain conversion voltage range (3) 0 (v ssa or v ref- tied to ground) v ref+ v r ain (2) external input impedance see equation 1 and ta bl e 6 0 for details 50 k r adc (2) sampling switch resistance 1 k c adc (2) internal sample and hold capacitor 8pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc t lat (2) injection trigger conversion latency f adc = 14 mhz 0.214 s 3 (4) 1/f adc t latr (2) regular trigger conversion latency f adc = 14 mhz 0.143 s 2 (4) 1/f adc t s (2) sampling time f adc = 14 mhz 0.107 17.1 s 1.5 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. based on characterization, not tested in production. 2. guaranteed by design, not tested in production. 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 3: pinouts and pin descriptions for further details. 4. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 59 .
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 104/130 doc id 14611 rev 8 equation 1: r ain max formula the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 60. r ain max for f adc = 14 mhz (1) 1. guaranteed by design, not tested in production. t s (cycles) t s (s) r ain max (k ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na table 61. adc accuracy - limited test conditions (1)(2) 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 5.3.14 does not affect the adc accuracy. symbol parameter test conditions typ max (3) 3. based on characterisation , not tested in production. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 3 v to 3.6 v t a = 25 c measurements made after adc calibration v ref+ = v dda 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 r ain t s f adc c adc 2 n2 + () ln ------------------------------------------------------------- - r adc ? <
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 105/130 figure 57. adc accuracy characteristics table 62. adc accuracy (1) (2)(3) 1. adc dc accuracy values are m easured after internal calibration. 2. better performance could be achieved in restricted v dd , frequency, v ref and temperature ranges. 3. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 5.3.14 does not affect the adc accuracy. symbol parameter test conditions typ max (4) 4. based on characterisation , not tested in production. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 2.4 v to 3.6 v measurements made after adc calibration 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal =
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 106/130 doc id 14611 rev 8 figure 58. typical connection diagram using the adc 1. refer to ta b l e 5 9 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 59 or figure 60 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 59. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. ai14150c stm32f103xx v dd ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc (1) 12-bit converter c adc (1) sample and hold adc converter v ref+ (see note 1) stm32f103xx v dda v ssa /v ref? (see note 1) 1 f // 10 nf 1 f // 10 nf ai14388b
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 107/130 figure 60. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. v ref+ /v dda stm32f103xx 1 f // 10 nf v ref? /v ssa ai14389 (see note 1) (see note 1)
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 108/130 doc id 14611 rev 8 5.3.20 dac elect rical specifications table 63. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 2.4 3.6 v v ref+ reference supply voltage 2.4 3.6 v v ref+ must always be below v dda v ssa ground 0 0 v r load (1) resistive load with buffer on 5 k r o (1) impedance output with buffer off 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (1) capacitive load 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x155) and (0xeab) at v ref+ = 2.4 v dac_out max (1) higher dac_out voltage with buffer on v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off 0.5 mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off v ref+ ? 1lsb v i ddvref+ dac dc current consumption in quiescent mode (standby mode) 220 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda dac dc current consumption in quiescent mode (standby mode) 380 a with no load, middle code (0x800) on the inputs 480 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (2) differential non linearity difference between two consecutive code-1lsb) 0.5 lsb given for the dac in 10-bit configuration 2 lsb given for the dac in 12-bit configuration inl (2) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) 1 lsb given for the dac in 10-bit configuration 4 lsb given for the dac in 12-bit configuration
stm32f103xc, stm32f103xd, stm32f103xe electrical characteristics doc id 14611 rev 8 109/130 figure 61. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. offset (2) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) 10 mv given for the dac in 12-bit configuration 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v 12 lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (2) gain error 0.5 % given for the dac in 12bit configuration t settling (2) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb 34 sc load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) 1ms/sc load 50 pf, r load 5 k t wakeup (2) wakeup time from off state (setting the enx bit in the dac control register) 6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement ?67 ?40 db no r load , c load = 50 pf 1. guaranteed by design, not tested in production. 2. guaranteed by characterizati on, not tested in production. table 63. dac characteristics (continued) symbol parameter min typ max unit comments r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157
electrical characteristics stm32f103xc, stm32f103xd, stm32f103xe 110/130 doc id 14611 rev 8 5.3.21 temperature sen sor characteristics table 64. ts characteristics symbol parameter min typ max unit t l v sense linearity with temperature 1 2c avg_slope average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) 1. guaranteed by design, not tested in production. startup time 4 10 s t s_temp (2)(1) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 s
stm32f103xc, stm32f103xd, stm32f103xe package characteristics doc id 14611 rev 8 111/130 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package characteristics stm32f103xc, stm32f103xd, stm32f103xe 112/130 doc id 14611 rev 8 figure 62. bga pad footprint table 65. recommended pcb design rules (0.80/0.75 mm pitch bga) dimension recommended values dpad ? = 0.37 mm dsm ? = 0.52 mm typ. (depends on solder mask registration tolerance) solder paste 0.37 mm aperture diameter ? non solder mask defined pads are recommended ? 4 to 6 mils screen print $pad $sm -36
stm32f103xc, stm32f103xd, stm32f103xe package characteristics doc id 14611 rev 8 113/130 figure 63. lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline 1. drawing is not to scale. table 66. lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max typ min max a1.700.0669 a1 0.21 0.0083 a2 1.07 0.0421 a3 0.27 0.0106 a4 0.85 0.0335 b 0.35 0.40 0.45 0.0138 0.0157 0.0177 d 9.85 10.00 10.15 0. 3878 0.3937 0.3996 d1 8.80 0.3465 e 9.85 10.00 10.15 0. 3878 0.3937 0.3996 e1 8.80 0.3465 e0.80 0.0315 f0.60 0.0236 ddd 0.10 0.0039 eee 0.15 0.0059 fff 0.08 0.0031 s e a ting pl a ne c a2 a4 a 3 c ddd a1 a b a d1 e f d f e1 e e m eee m cab c fff (144 ba ll s ) ? b m ? ? x 3 _me b a ll a1
package characteristics stm32f103xc, stm32f103xd, stm32f103xe 114/130 doc id 14611 rev 8 figure 64. lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package outline 1. drawing is not to scale. table 67. lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.700 0.0669 a1 0.270 0.0106 a2 1.085 0.0427 a3 0.30 0.0118 a4 0.80 0.0315 b 0.45 0.50 0.55 0.0177 0.0197 0.0217 d 9.85 10.00 10.15 0.3878 0.3937 0.3996 d1 7.20 0.2835 e 9.85 10.00 10.15 0.3878 0.3937 0.3996 e1 7.20 0.2835 e 0.80 0.0315 f 1.40 0.0551 ddd 0.12 0.0047 eee 0.15 0.0059 fff 0.08 0.0031
stm32f103xc, stm32f103xd, stm32f103xe package characteristics doc id 14611 rev 8 115/130 figure 65. wlcsp, 64-ball 4.466 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline 1. drawing is not to scale. 2. primary datum z and seating plane are defined by the spherical crowns of the ball. table 68. wlcsp, 64-ball 4.466 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.535 0.585 0.635 0.0211 0.0230 0.0250 a1 0.205 0.230 0.255 0.0081 0.0091 0.0100 a2 0.330 0.355 0.380 0.0130 0.0140 0.0150 b (2) 2. dimension is measured at the maximum ba ll diameter parallel to primary datum z. 0.290 0.320 0.350 0.0114 0.0126 0.0138 e 0.500 0.0197 e1 3.500 0.1378 f 0.447 0.0176 g 0.483 0.0190 d 4.446 4.466 4.486 0.1750 0.1758 0.1766 e 4.375 4.395 4.415 0.1722 0.1730 0.1738 h 0.250 0.0098 l 0.200 0.0079 eee 0.05 0.0020 aaa 0.10 0.0039 number of balls 64 a b c d e f g h 1 2 3 4 5 6 7 8 detail a side view ball side wafer back side marking area a1 ball corner a a2 a1 ball corner notch ball a1 b seating plane (see note 2) detail a rotated 90 ? cr_me e e e1 e1 f g d e aaa eee h l l
package characteristics stm32f103xc, stm32f103xd, stm32f103xe 116/130 doc id 14611 rev 8 figure 66. bga pad footprint table 69. recommended pcb design rules (0.5mm pitch bga) dimension recommended values dpad ? = 300 m (circular) - 250 m recommended dsm ? = 340 m min (for 300 m diameter pad) pcd pad size cu - ni (2-6 m) - au (0.2 m max) ? non solder mask defined ? micro via under bump allowed $pad $sm -36
stm32f103xc, stm32f103xd, stm32f103xe package characteristics doc id 14611 rev 8 117/130 figure 67. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline (1) figure 68. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 ai149 1 36 37 72 73 108 109 144 table 70. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a1.600.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 21.80 22.00 22.20 0.8583 0.8661 0.874 d1 19.80 20.00 20.20 0.7795 0.7874 0.7953 d3 17.50 0.689 e 21.80 22.00 22.20 0.8583 0.8661 0.874 e1 19.80 20.00 20.20 0.7795 0.7874 0.7953 e3 17.50 0.689 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f103xc, stm32f103xd, stm32f103xe 118/130 doc id 14611 rev 8 figure 69. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline (1) figure 70. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0. 3 16.7 14. 3 100 26 12. 3 25 1.2 16.7 1 a i14906 b table 71. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 15.80 16.00 16.20 0.622 0.6299 0.6378 d1 13.80 14.00 14.20 0.5433 0.5512 0.5591 d3 12.00 0.4724 e 15.80 16.00 16.20 0.622 0.6299 0.6378 e1 13.80 14.00 14.20 0.5433 0.5512 0.5591 e3 12.00 0.4724 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f103xc, stm32f103xd, stm32f103xe package characteristics doc id 14611 rev 8 119/130 figure 71. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline (1) figure 72. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. 5w_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 72. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d. 7.500 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.00 10.200 0.3858 0.3937 0.4016 e 0.500 0.0197 k 03.57 03.57 l 0.450 0.600 0.75 0.0177 0.0236 0.0295 l1 1.000 0.0394 ccc 0.080 0.0031 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f103xc, stm32f103xd, stm32f103xe 120/130 doc id 14611 rev 8 6.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 10: general operating conditions on page 42 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 6.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org table 73. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lfbga144 - 10 10 mm / 0.8 mm pitch 40 c/w thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 30 thermal resistance junction-ambient lfbga100 - 10 10 mm / 0.8 mm pitch 40 thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 thermal resistance junction-ambient wlcsp64 50
stm32f103xc, stm32f103xd, stm32f103xe package characteristics doc id 14611 rev 8 121/130 6.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 74: ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f103xc, stm32f103xd and stm32f103xe at maximum dissipation, it is useful to calculate the exact power consumption and junction temper ature to determine which te mperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in ta b l e 7 3 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 82 c + (46 c/w 447 mw) = 82 c + 20.6 c = 102.6 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see table 74: ordering information scheme ). example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw
package characteristics stm32f103xc, stm32f103xd, stm32f103xe 122/130 doc id 14611 rev 8 using the values obtained in ta b l e 7 3 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 115 c + (46 c/w 134 mw) = 115 c + 6.2 c = 121.2 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see table 74: ordering information scheme ). figure 73. lqfp100 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 t a (c) p d (mw) suffix 6 suffix 7
stm32f103xc, stm32f103xd, stm32f103xe part numbering doc id 14611 rev 8 123/130 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 74. ordering information scheme example: stm32 f 103 r c t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 103 = performance line pin count r = 64 pins v = 100 pins z = 144 pins flash memory size c = 256 kbytes of flash memory d = 384 kbytes of flash memory e = 512 kbytes of flash memory package h = bga t = lqfp y = wlcsp64 temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and real
revision history stm32f103xc, stm32f103xd, stm32f103xe 124/130 doc id 14611 rev 8 8 revision history table 75. document revision history date revision changes 07-apr-2008 1 initial release. 22-may-2008 2 document status promoted from ta rget specification to preliminary data. section 1: introduction and section 2.2: full compatibility throughout the family modified. small text changes. note 2 added in table 2: stm32f103xc, stm32f103xd and stm32f103xe features and peripheral counts on page 11 . lqpf100/bga100 column added to table 6: fsmc pin definition on page 36 . values and figures added to maximum current consumption on page 44 (see ta b l e 1 4 , ta b l e 1 5 , ta b l e 1 6 and ta b l e 1 7 and see figure 14 , figure 15 , figure 17 , figure 18 and figure 19 ). values added to typical current consumption on page 52 (see ta bl e 1 8 , ta b l e 1 9 and ta b l e 2 0 ). table 19: typical current consumption in standby mode removed. note 4 and note 1 added to table 57: usb dc electrical characteristics and table 58: usb: full-speed electrical characteristics on page 102 , respectively. v usb added to table 57: usb dc electrical characteristics on page 102 . figure 68: recommended footprint(1) on page 117 corrected. equation 1 corrected. figure 73: lqfp100 pd max vs. ta on page 122 modified. tolerance values corrected in table 66: lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data on page 113 .
stm32f103xc, stm32f103xd, stm32f103xe revision history doc id 14611 rev 8 125/130 21-jul-2008 3 document status promoted from pr eliminary data to full datasheet. fsmc (flexible static memory controller) on page 15 modified. number of complementary channels corrected in figure 1: stm32f103xc, stm32f103xd and stm32f103xe performance line block diagram . power supply supervisor on page 17 modified and v dda added to table 10: general operating conditions on page 42 . table notes revised in section 5: electrical characteristics . capacitance modified in figure 12: power supply scheme on page 40 . table 52: scl frequency (fpclk1= 36 mhz.,vdd = 3.3 v) updated. table 53: spi characteristics modified, t h(nss) modified in figure 49: spi timing diagram - slave mode and cpha = 0 on page 96 . minimum sda and scl fall time value for fast mode removed from table 51: i2c characteristics on page 93 , note 1 modified. i dd_vbat values and some i dd values with regulator in run mode added to table 17: typical and maximum curr ent consumptions in stop and standby modes on page 48 . table 30: flash memory endurance and data retention on page 63 updated. t su(nss) modified in table 53: spi characteristics on page 95 . eo corrected in table 62: adc accuracy on page 105 . figure 58: typical connection diagram using the adc on page 106 and note below corrected. typical t s_temp value removed from table 64: ts characteristics on page 110 . section 6.1: package mechanical data on page 111 updated. small text changes. table 75. document revision history date revision changes
revision history stm32f103xc, stm32f103xd, stm32f103xe 126/130 doc id 14611 rev 8 12-dec-2008 4 timers specified on page 1 (motor control capability mentioned). section 2.2: full compatibility throughout the family updated. table 4: high-density timer feature comparison added. general-purpose timers (timx) and advanced-control timers (tim1 and tim8) on page 19 updated. figure 1: stm32f103xc, st m32f103xd and stm32f103xe performance line block diagram modified. note 10 added, main function after reset and note 5 on page 35 updated in table 5: high-density stm32f103xx pin definitions . note 2 modified below table 7: voltage characteristics on page 41 , | v ddx | min and | v ddx | min removed. note 2 and p d values for lqfp144 and lfbga144 packages added to table 10: general operating conditions on page 42 . measurement conditions specified in section 5.3.5: supply current characteristics on page 44 . max values at t a = 85 c and t a = 105 c updated in table 17: typical and maximum current consumptions in stop and standby modes on page 48 . section 5.3.10: fsmc characteristics on page 63 updated. data added to table 42: emi characteristics on page 84 . i vref added to table 59: adc characteristics on page 103 . table 73: package thermal characteristics on page 120 updated. small text changes. table 75. document revision history date revision changes
stm32f103xc, stm32f103xd, stm32f103xe revision history doc id 14611 rev 8 127/130 30-mar-2009 5 i/o information clarified on page 1 . figure 4: stm32f103xc and stm32f103xe performanc e line bga100 ballout corrected. i/o information clarified on page 1 . in table 5: high-density stm32f103xx pin definitions : ? i/o level of pins pf11, pf12, pf13, pf14, pf15, g0, g1 and g15 updated ? pb4, pb13, pb14, pb15, pb3/tr aceswo moved from default column to remap column pg14 pin description modified in table 6: fsmc pin definition . figure 9: memory map on page 38 modified. note modified in table 14: maximum current consumption in run mode, code with data processing running from flash and table 16: maximum current consumption in sleep mode, code running from flash or ram . figure 17 , figure 18 and figure 19 show typical curves (titles changed). table 21: high-speed external user clock characteristics and ta b l e 2 2 : low-speed external user clock characteristics modified. acc hsi max values modified in table 25: hsi oscillator characteristics . fsmc configuration modified for asynchronous waveforms and timings . notes modified below figure 24: asynchronous non-multiplexed sram/psram/nor read waveforms and figure 25: asynchronous non-multiplexed sram/psram/nor write waveforms . t w(nadv) values modified in table 31: asynchronous non-multiplexed sram/psram/nor read timings and table 34: asynchronous multiplexed psram/nor write timings . t h(data_nwe) modified in table 32: asynchronous non-multiplexed sram/psram/nor write timings in table 36: synchronous multiplexed psram write timings and table 38: synchronous non-multiplexed psram write timings : ?t v(data-clk) renamed as t d(clkl-data) ?t d(clkl-data) min value removed and max value added ?t h(clkl-dv) / t h(clkl-adv) removed figure 28: synchronous multiplexed nor/psram read timings , figure 29: synchronous multiplexed psram write timings and figure 31: synchronous non-multiplexed psram write timings modified. figure 52: i2s slave timing diagram (philips protocol)(1) and figure 53: i2s master timing diagram (philips protocol)(1) modified. wlcsp64 package added (see figure 8: stm32f103xc and stm32f103xe performance lin e wlcsp64 ballout, ball side , ta b l e 5 : high-density stm32f103xx pin definitions , figure 65: wlcsp, 64-ball 4.466 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline and table 68: wlcsp, 64-ball 4.466 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data ). small text changes. table 75. document revision history date revision changes
revision history stm32f103xc, stm32f103xd, stm32f103xe 128/130 doc id 14611 rev 8 21-jul-2009 6 figure 1: stm32f103xc, st m32f103xd and stm32f103xe performance line block diagram updated. note 5 updated and note 4 added in table 5: high-density stm32f103xx pin definitions . v rerint and t coeff added to table 13: embedded internal reference voltage . table 16: maximum current consumpt ion in sleep mode, code running from flash or ram modified. f hse_ext min modified in table 21: high-speed external user clock characteristics . c l1 and c l2 replaced by c in table 23: hse 4-16 mhz oscillator characteristics and table 24: lse oscillator characteristics (flse = 32.768 khz) , notes modified and moved below the tables. note 1 modified below figure 22: typical application with an 8 mhz crystal . table 25: hsi oscillator characteristics modified. conditions removed from table 27: low-power mode wakeup timings . jitter added to table 28: pll characteristics . figure 47: recommended nrst pin protection modified. in table 31: asynchronous non-multiplexed sram/psram/nor read timings : t h(bl_noe) and t h(a_noe) modified. in table 32: asynchronous non-multiplexed sram/psram/nor write timings : t h(a_nwe) and t h(data_nwe) modified. in table 33: asynchronous multiplexed psram/nor read timings : t h(ad_nadv) and t h(a_noe) modified. in table 34: asynchronous multiplexed psram/nor write timings : t h(a_nwe) modified. in table 35: synchronous multiplexed nor/psram read timings : t h(clkh-nwaitv) modified. in table 40: switching characteristics for nand flash read and write cycles : t h(noe-d) modified. table 53: spi characteristics modified. values added to table 54: i2s characteristics and table 55: sd / mmc characteristics . c adc and r ain parameters modified in table 59: adc characteristics . r ain max values modified in table 60: rain max for fadc = 14 mhz . table 63: dac characteristics modified. figure 61: 12-bit buffered /non- buffered dac added. figure 64: lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package outline and table 67: lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data updated. 24-sep-2009 7 number of dacs corrected in table 3: stm32f103xx family . i dd_vbat updated in table 17: typical and maximum current consumptions in stop and standby modes . figure 16: typical current consumption on vbat with rtc on vs. temperature at different vbat values added. iec 1000 standard updated to iec 61000 and sae j1752/3 updated to iec 61967-2 in section 5.3.11: emc characteristics on page 83 . table 63: dac characteristics modified. small text changes. table 75. document revision history date revision changes
stm32f103xc, stm32f103xd, stm32f103xe revision history doc id 14611 rev 8 129/130 19-apr-2011 8 updated package choice for 103rx in ta b l e 2 updated footnotes below table 7: voltage characteristics on page 41 and table 8: current characteristics on page 41 updated tw min in table 21: high-speed external user clock characteristics on page 55 updated startup time in table 24: lse oscillator characteristics (flse = 32.768 khz) on page 59 updated note 2 in table 51: i2c characteristics on page 93 updated figure 48: i2c bus ac waveforms and measurement circuit updated figure 47: recommended nrst pin protection updated section 5.3.14: i/o port characteristics updated table 31: asynchronous non-multiplexed sram/psram/nor read timings on page 64 updated fsmc figure 28 thru figure 31 updated figure 41: nand controller waveforms for common memory write access and table 40: switching characteristics for nand flash read and write cycl es on page 82 added section 5.3.13: i/o current inje ction characteristics on page 85 updated figure 66 and added table 69: recommended pcb design rules (0.5mm pitch bga) on page 116 lqfp64 package mechanical data updated: see figure 71: lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline and ta b l e 7 2 : lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . table 75. document revision history date revision changes
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